Datasheet

1. Write any value to either of the registers OCR2 or TCCR2.
2. Wait for the corresponding Update Busy Flag to be cleared.
3. Read TCNT2.
• During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous
timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least
one before the processor can read the timer value causing the setting of the Interrupt Flag. The
Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock.
20.10. Timer/Counter Prescaler
Figure 20-12. Prescaler for Timer/Counter2
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
clk
I/O
clk
T2S
TOS C1
AS2
CS 20
CS 21
CS 22
clk
T2S
/8
clk
T2S
/64
clk
T2S
/128
clk
T2S
/1024
clk
T2S
/256
clk
T2S
/32
0
PS R2
Clea r
clk
T2
The clock source for Timer/Counter2 is named clk
T2S
. clk
T2S
is by default connected to the main system
clock clk
I/O
. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1
pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1
and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and
TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for
use with a 32.768kHz crystal. Applying an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clk
T2S
/8, clk
T2S
/32, clk
T2S
/64, clk
T2S
/128,
clk
T2S
/256, and clk
T2S
/1024. Additionally, clk
T2S
as well as 0 (stop) may be selected. Setting the PSR2 bit
in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler.
20.11. Register Description
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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