Datasheet

continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM
mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in the timing diagram above OCn has a transition from high to low even
though there is no Compare Match. The point of this transition is to guarantee symmetry around
BOTTOM. There are two cases that give a transition without Compare Match:
• OCR2A changes its value from MAX, like in the timing diagram above. When the OCR2A value is MAX
the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry
around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare
Match.
• The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the
Compare Match and hence the OCn change that would have happened on the way up.
20.8. Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clk
T2
) is
therefore shown as a clock enable signal. In Asynchronous mode, clk
I/O
should be replaced by the Timer/
Counter Oscillator clock. The figures include information on when Interrupt Flags are set. The following
figure contains timing data for basic Timer/Counter operation. The figure shows the count sequence close
to the MAX value in all modes other than phase correct PWM mode.
Figure 20-8. Timer/Counter Timing Diagram, no Prescaling
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
The next figure shows the same timing data, but with the prescaler enabled.
Figure 20-9. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
The next figure shows the setting of OCF2 in all modes except CTC mode.
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