Datasheet

20.2.1. Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request
(shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are
individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in
the figure since these registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the
TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the
Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the
Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock
source is selected. The output from the clock select logic is referred to as the timer clock (clk
T2
).
The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all
times. The result of the compare can be used by the waveform generator to generate a PWM or variable
frequency output on the Output Compare Pin (OC2). For details, see Output Compare Unit. The Compare
Match event will also set the Compare Flag (OCF2) which can be used to generate an Output Compare
interrupt request.
20.2.2. Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces
the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program,
the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2 counter value and so on).
The definitions in the following table are also used extensively throughout the document.
Table 20-1. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX)
or the value stored in the OCR2 Register. The assignment is dependent on the
mode of operation.
20.3. Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source.
The clock source clk
T2
is by default equal to the MCU clock, clk
I/O
. When the AS2 bit in the ASSR
Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to
TOSC1 and TOSC2. For details on asynchronous operation, refer to Asynchronous Operation of the
Timer/Counter. For details on clock sources and prescaler, refer to Timer/Counter Prescaler.
Related Links
Timer/Counter0 and Timer/Counter1 Prescalers on page 102
20.4. Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. The following
figure shows a block diagram of the counter and its surrounding environment.
Atmel ATmega32A [DATASHEET]
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