Datasheet

19.11.2. TCCR1B – Timer/Counter1 Control Register B
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Name: TCCR1B
Offset: 0x2E
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x4E
Bit 7 6 5 4 3 2 1 0
ICNC1 ICES1 WGM13 WGM12 CS12 CS11 CS10
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated,
the input from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal
valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four
Oscillator cycles when the noise canceler is enabled.
Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When
the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is
written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input
Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to
cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and
the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is
disabled.
Bit 4 – WGM13: Waveform Generation Mode
Refer to TCCR1A.
Bit 3 – WGM12: Waveform Generation Mode
Refer to TCCR1A.
Bits 2:0 – CS1n: Clock Select [n = 0:2]
The three Clock Select bits select the clock source to be used by the Timer/Counter. Refer to figures
Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling and Timer/Counter Timing Diagram,
Setting of OCF1x, with Prescaler (f
clk_I/O
/8).
Table 19-6. Clock Select Bit Description
CA12 CA11 CS10 Description
0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clk
I/O
/1 (No prescaling)
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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