Datasheet

If OCRnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, the OCnA output will
toggle with a 50% duty cycle.
19.10. Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
Tn
) is therefore shown as a clock
enable signal in the following figures. The figures include information on when Interrupt Flags are set, and
when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double
buffering). The next figure shows a timing diagram for the setting of OCFnx.
Figure 19-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
clk
Tn
(clk
I/O
/1)
OCFnx
clk
I/O
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
The next figure shows the same timing data, but with the prescaler enabled.
Figure 19-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f
clk_I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
The next figure shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be
the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same
renaming applies for modes that set the TOVn Flag at BOTTOM.
Atmel ATmega32A [DATASHEET]
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