Datasheet

PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that
use dual-slope operation. This high frequency makes the fast PWM mode well suited for power
regulation, rectification, and DAC applications. High frequency allows physically small sized external
components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA.
The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is
16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following
equation:

FPWM
=
log TOP+1
log 2
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed
values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the
value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle. The
timing diagram for the fast PWM mode is shown in the figure below. The figure shows fast PWM mode
when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a
histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches
between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a Compare Match occurs.
Figure 19-7. Fast PWM Mode, Timing Diagram
TCNTn
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 7
Period
2 3 4 5 6 8
OCnx
OCnx
(COMnx[1:0] = 0x2)
(COMnx[1:0] = 0x3)
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the
OCFnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is
used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be
used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the
value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a
Compare Match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP
values the unused bits are masked to zero when any of the OCRnx Registers are written.
The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value.
The ICRn Register is not double buffered. This means that if ICRn is changed to a low value when the
counter is running with none or a low prescaler value, there is a risk that the new ICRn value written is
lower than the current value of TCNTn. The result will then be that the counter will miss the Compare
Match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around
starting at 0x0000 before the Compare Match can occur. The OCRnA Register, however, is double
buffered. This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O location
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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