Datasheet

19.7.2. Compare Match Blocking by TCNTn Write
All CPU writes to the TCNTn Register will block any Compare Match that occurs in the next timer clock
cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as
TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.
19.7.3. Using the Output Compare Unit
Since writing TCNTn in any mode of operation will block all compare matches for one timer clock cycle,
there are risks involved when changing TCNTn when using any of the Output Compare channels,
independent of whether the Timer/Counter is running or not. If the value written to TCNTn equals the
OCRnx value, the Compare Match will be missed, resulting in incorrect waveform generation. Do not
write the TCNTn equal to TOP in PWM modes with variable TOP values. The Compare Match for the
TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNTn value
equal to BOTTOM when the counter is downcounting.
The setup of the OCnx should be performed before setting the Data Direction Register for the port pin to
output. The easiest way of setting the OCnx value is to use the Force Output Compare (FOCnx) strobe
bits in Normal mode. The OCnx Register keeps its value even when changing between Waveform
Generation modes.
Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the
COMnx1:0 bits will take effect immediately.
19.8. Compare Match Output Unit
The Compare Output mode (COMnx1:0) bits have two functions. The waveform generator uses the
COMnx1:0 bits for defining the Output Compare (OCnx) state at the next Compare Match. Secondly the
COMnx1:0 bits control the OCnx pin output source. The figure below shows a simplified schematic of the
logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are
shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected
by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx
Register, not the OCnx pin. If a System Reset occur, the OCnx Register is reset to “0”.
Figure 19-5. Compare Match Output Unit, Schematic
PORT
DDR
D Q
D Q
OCnx
Pin
OCnx
D Q
Waveform
Generator
COMnx[1]
COMnx[0]
0
1
DATA BUS
FOCnx
clk
I/O
Atmel ATmega32A [DATASHEET]
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