Datasheet

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Table Of Contents

Introduction
Features
Table of Contents
1. Description
2. Configuration Summary
3. Ordering Information
4. Block Diagram
5. Pin Configurations
- 5.1. VCC
- 5.2. GND
- 5.3. PortA (PA7:PA0)
- 5.4. Port B (PB7:PB0)
- 5.5. Port C (PC7:PC0)
- 5.6. Port D (PD7:PD0)
- 5.7. RESET
- 5.8. XTAL1
- 5.9. XTAL2
- 5.10. AVCC
- 5.11. AREF
6. Resources
7. Data Retention
8. About Code Examples
9. Capacitive Touch Sensing
10. AVR CPU Core
- 10.1. Overview
- 10.2. ALU – Arithmetic Logic Unit
- 10.3. Status Register
  - 10.3.1. SREG – The AVR Status Register
- 10.4. General Purpose Register File
  - 10.4.1. The X-register, Y-register and Z-register
- 10.5. Stack Pointer
- 10.6. Instruction Execution Timing
- 10.7. Reset and Interrupt Handling
  - 10.7.1. Interrupt Response Time
11. AVR Memories
- 11.1. Overview
- 11.2. In-System Reprogrammable Flash Program Memory
- 11.3. SRAM Data Memory
  - 11.3.1. Data Memory Access Times
- 11.4. EEPROM Data Memory
- 11.5. I/O Memory
- 11.6. Register Description
12. System Clock and Clock Options
- 12.1. Clock Systems and their Distribution
- 12.2. Clock Sources
- 12.3. Default Clock Source
- 12.4. Crystal Oscillator
- 12.5. Low-frequency Crystal Oscillator
- 12.6. External RC Oscillator
- 12.7. Calibrated Internal RC Oscillator
- 12.8. External Clock
- 12.9. Timer/Counter Oscillator
- 12.10. Register Description
  - 12.10.1. OSCCAL – The Oscillator Calibration Register
13. Power Management and Sleep Modes
- 13.1. Sleep Modes
- 13.2. Idle Mode
- 13.3. ADC Noise Reduction Mode
- 13.4. Power-down Mode
- 13.5. Power-save Mode
- 13.6. Standby Mode
- 13.7. Extended Standby Mode
- 13.8. Minimizing Power Consumption
- 13.9. Register Description
  - 13.9.1. MCUCR – MCU Control Register
14. System Control and Reset
- 14.1. Resetting the AVR
- 14.2. Reset Sources
- 14.3. Internal Voltage Reference
  - 14.3.1. Voltage Reference Enable Signals and Start-up Time
- 14.4. Watchdog Timer
- 14.5. Register Description
  - 14.5.1. MCUCSR – MCU Control and Status Register
  - 14.5.2. WDTCR – Watchdog Timer Control Register
15. Interrupts
- 15.1. Interrupt Vectors in ATmega32A
  - 15.1.1. Moving Interrupts Between Application and Boot Space
- 15.2. Register Description
  - 15.2.1. GICR – General Interrupt Control Register
16. External Interrupts
- 16.1. Register Description
17. I/O Ports
- 17.1. Overview
- 17.2. Ports as General Digital I/O
- 17.3. Alternate Port Functions
- 17.4. Register Description
18. Timer/Counter0 and Timer/Counter1 Prescalers
- 18.1. Overview
- 18.2. Internal Clock Source
- 18.3. Prescaler Reset
- 18.4. External Clock Source
- 18.5. Register Description
  - 18.5.1. SFIOR – Special Function IO Register
19. 16-bit Timer/Counter1
- 19.1. Features
- 19.2. Overview
- 19.3. Accessing 16-bit Registers
  - 19.3.1. Reusing the Temporary High Byte Register
- 19.4. Timer/Counter Clock Sources
- 19.5. Counter Unit
- 19.6. Input Capture Unit
- 19.7. Output Compare Units
- 19.8. Compare Match Output Unit
  - 19.8.1. Compare Output Mode and Waveform Generation
- 19.9. Modes of Operation
- 19.10. Timer/Counter Timing Diagrams
- 19.11. Register Description
20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 20.1. Features
- 20.2. Overview
  - 20.2.1. Registers
  - 20.2.2. Definitions
- 20.3. Timer/Counter Clock Sources
- 20.4. Counter Unit
- 20.5. Output Compare Unit
- 20.6. Compare Match Output Unit
  - 20.6.1. Compare Output Mode and Waveform Generation
- 20.7. Modes of Operation
- 20.8. Timer/Counter Timing Diagrams
- 20.9. Asynchronous Operation of the Timer/Counter
  - 20.9.1. Asynchronous Operation of Timer/Counter2
- 20.10. Timer/Counter Prescaler
- 20.11. Register Description
21. 8-bit Timer/Counter0 with PWM
- 21.1. Features
- 21.2. Overview
  - 21.2.1. Registers
  - 21.2.2. Definitions
- 21.3. Timer/Counter Clock Sources
- 21.4. Counter Unit
- 21.5. Output Compare Unit
- 21.6. Compare Match Output Unit
  - 21.6.1. Compare Output Mode and Waveform Generation
- 21.7. Modes of Operation
- 21.8. Timer/Counter Timing Diagrams
- 21.9. Register Description
22. SPI – Serial Peripheral Interface
- 22.1. Features
- 22.2. Overview
- 22.3. SS Pin Functionality
  - 22.3.1. Slave Mode
  - 22.3.2. Master Mode
- 22.4. Data Modes
- 22.5. Register Description
23. USART - Universal Synchronous and Asynchronous serial Receiver and Transmitter
- 23.1. Features
- 23.2. Overview
  - 23.2.1. AVR USART vs. AVR UART – Compatibility
- 23.3. Clock Generation
- 23.4. Frame Formats
  - 23.4.1. Parity Bit Calculation
- 23.5. USART Initialization
- 23.6. Data Transmission – The USART Transmitter
- 23.7. Data Reception – The USART Receiver
- 23.8. Asynchronous Data Reception
- 23.9. Multi-Processor Communication Mode
  - 23.9.1. Using MPCM
- 23.10. Accessing UBRRH/UCSRC Registers
  - 23.10.1. Write Access
  - 23.10.2. Read Access
- 23.11. Register Description
- 23.12. Examples of Baud Rate Setting
24. TWI - Two-wire Serial Interface
- 24.1. Features
- 24.2. Overview
- 24.3. Two-Wire Serial Interface Bus Definition
  - 24.3.1. TWI Terminology
  - 24.3.2. Electrical Interconnection
- 24.4. Data Transfer and Frame Format
- 24.5. Multi-master Bus Systems, Arbitration and Synchronization
- 24.6. Using the TWI
- 24.7. Multi-master Systems and Arbitration
- 24.8. Register Description
25. AC - Analog Comparator
- 25.1. Overview
- 25.2. Analog Comparator Multiplexed Input
- 25.3. Register Description
  - 25.3.1. SFIOR – Analog Comparator Control and Status Register
  - 25.3.2. ACSR – Analog Comparator Control and Status Register
26. ADC - Analog to Digital Converter
- 26.1. Features
- 26.2. Overview
- 26.3. Starting a Conversion
- 26.4. Prescaling and Conversion Timing
  - 26.4.1. Differential Gain Channels
- 26.5. Changing Channel or Reference Selection
  - 26.5.1. ADC Input Channels
  - 26.5.2. ADC Voltage Reference
- 26.6. ADC Noise Canceler
- 26.7. ADC Conversion Result
- 26.8. Register Description
27. JTAG Interface and On-chip Debug System
- 27.1. Features
- 27.2. Overview
- 27.3. TAP – Test Access Port
- 27.4. TAP Controller
- 27.5. Using the Boundary-scan Chain
- 27.6. Using the On-chip Debug System
- 27.7. On-chip Debug Specific JTAG Instructions
- 27.8. Using the JTAG Programming Capabilities
- 27.9. Bibliography
- 27.10. IEEE 1149.1 (JTAG) Boundary-scan
  - 27.10.1. Features
  - 27.10.2. System Overview
- 27.11. Data Registers
- 27.12. Boundry-scan Specific JTAG Instructions
- 27.13. Boundary-scan Chain
- 27.14. ATmega32A Boundary-scan Order
- 27.15. Boundary-scan Description Language Files
- 27.16. Register Description
  - 27.16.1. OCDR – On-chip Debug Register
  - 27.16.2. MCUCSR – MCU Control and Status Register
28. BTLDR - Boot Loader Support – Read-While-Write Self-Programming
- 28.1. Features
- 28.2. Overview
- 28.3. Application and Boot Loader Flash Sections
  - 28.3.1. Application Section
  - 28.3.2. BLS – Boot Loader Section
- 28.4. Read-While-Write and No Read-While-Write Flash Sections
  - 28.4.1. RWW – Read-While-Write Section
  - 28.4.2. NRWW – No Read-While-Write Section
- 28.5. Boot Loader Lock Bits
- 28.6. Entering the Boot Loader Program
- 28.7. Addressing the Flash During Self-Programming
- 28.8. Self-Programming the Flash
- 28.9. Register Description
  - 28.9.1. SPMCR – Store Program Memory Control Register
29. Memory Programming
- 29.1. Program and Data Memory Lock Bits
- 29.2. Fuse Bits
  - 29.2.1. Latching of Fuses
- 29.3. Signature Bytes
- 29.4. Signature Bytes
- 29.5. Calibration Byte
- 29.6. Parallel Programming Parameters, Pin Mapping, and Commands
  - 29.6.1. Signal Names
- 29.7. Parallel Programming
- 29.8. Serial Downloading
- 29.9. Serial Programming Pin Mapping
- 29.10. Programming Via the JTAG Interface
30. Electrical Characteristics
- 30.1. DC Characteristics
- 30.2. Speed Grades
- 30.3. Clock Characteristics
  - 30.3.1. External Clock Drive Waveforms
  - 30.3.2. External Clock Drive
- 30.4. System and Reset Characteristics
- 30.5. Two-wire Serial Interface Characteristics
- 30.6. SPI Timing Characteristics
- 30.7. ADC Characteristics
31. Typical Characteristics
- 31.1. Active Supply Current
- 31.2. Idle Supply Current
- 31.3. Power-down Supply Current
- 31.4. Power-save Supply current
- 31.5. Standby Supply Current
- 31.6. Pin Pull-up
- 31.7. Pin Driver Strength
- 31.8. Pin Thresholds and Hysteresis
- 31.9. BOD Thresholds and Analog Comparator Offset
- 31.10. Internal Oscillator Speed
- 31.11. Current Consumption of Peripheral Units
- 31.12. Current Consumption in Reset and Reset Pulsewidth
32. Register Summary
33. Instruction Set Summary
34. Packaging Information
- 34.1. 44-pin TQFP
- 34.2. 40-pin PDIP
- 34.3. 44-pin VQFN
35. Errata
- 35.1. ATmega32A, rev. J to rev. K
- 35.2. ATmega32A, rev. G to rev. I
36. Datasheet Revision History
- 36.1. 8155I - 08/2016
- 36.2. 8155H - 08/2016
- 36.3. 8155G - 10/2015
- 36.4. 8155F - 08/2015
- 36.5. 8155E - 02/2014
- 36.6. 8155D – 10/2013
- 36.7. 8155C - 02/2011
- 36.8. 8155B – 07/2009
- 36.9. 8155A – 06/2008

Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively

changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each

capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been

read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a

logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not

required (if an interrupt handler is used).

19.7. Output Compare Units

The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If

TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag

(OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Compare Flag generates an

Output Compare interrupt. The OCFnx Flag is automatically cleared when the interrupt is executed.

Alternatively the OCFnx Flag can be cleared by software by writing a logical one to its I/O bit location. The

waveform generator uses the match signal to generate an output according to operating mode set by the

Waveform Generation mode (WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and

BOTTOM signals are used by the waveform generator for handling the special cases of the extreme

values in some modes of operation (See Modes of Operation.)

A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e. counter

resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms

generated by the waveform generator.

The figure below shows a block diagram of the Output Compare unit. The small “n” in the register and bit

names indicates the device number (n = n for Timer/Counter n), and the “x” indicates Output Compare

unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are

gray shaded.

Atmel ATmega32A [DATASHEET]

Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016

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