Datasheet

Input Capture interrupt. The ICFn Flag is automatically cleared when the interrupt is executed.
Alternatively the ICFn Flag can be cleared by software by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the Low byte
(ICRnL) and then the High byte (ICRnH). When the Low byte is read the High byte is copied into the High
byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP
Register.
The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn
Register for defining the counter’s TOP value. In these cases the Waveform Generation mode
(WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register. When writing the
ICRn Register the High byte must be written to the ICRnH I/O location before the Low byte is written to
ICRnL.
For more information on how to access the 16-bit registers refer to Accessing 16-bit Registers.
19.6.1. Input Capture Pin Source
The main trigger source for the Input Capture unit is the Input Capture Pin (ICPn). Timer/Counter 1 can
alternatively use the Analog Comparator Output as trigger source for the Input Capture unit. The Analog
Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in
the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can
trigger a capture. The Input Capture Flag must therefore be cleared after the change.
Both the Input Capture Pin (ICPn) and the Analog Comparator Output (ACO) inputs are sampled using
the same technique as for the Tn pin (see figure Tn Pin Sampling in section External Clock Source). The
edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted
before the edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform
Generation mode that uses ICRn to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICPn pin.
Related Links
External Clock Source on page 102
19.6.2. Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise
canceler input is monitored over four samples, and all four must be equal for changing the output that in
turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in Timer/Counter
Control Register B (TCCRnB). When enabled the noise canceler introduces additional four system clock
cycles of delay from a change applied to the input, to the update of the ICRn Register. The noise canceler
uses the system clock and is therefore not affected by the prescaler.
19.6.3. Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity for
handling the incoming events. The time between two events is critical. If the processor has not read the
captured value in the ICRn Register before the next event occurs, the ICRn will be overwritten with a new
value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in the interrupt handler
routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum
interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of
the other interrupt requests.
Atmel ATmega32A [DATASHEET]
Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016
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