8-Bit AVR Microcontroller ATmega32A DATASHEET COMPLETE Introduction ® The Atmel ATmega32A is a low-power CMOS 8-bit microcontroller based ® on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32A achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed.
• – Capacitive touch buttons, sliders and wheels – Atmel QTouch and QMatrix acquisition – Up to 64 sense channels Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – • • • • • 8-channel, 10-bit ADC • 8 Single-ended Channels • 7 Differential Channels in TQFP Package Only • 2 Differential Channels with Programmable Gain
Table of Contents Introduction......................................................................................................................1 Features.......................................................................................................................... 1 1. Description.................................................................................................................9 2. Configuration Summary............................................................................
11.5. I/O Memory.................................................................................................................................32 11.6. Register Description................................................................................................................... 32 12. System Clock and Clock Options............................................................................ 39 12.1. Clock Systems and their Distribution..............................................................
18.3. Prescaler Reset........................................................................................................................102 18.4. External Clock Source..............................................................................................................102 18.5. Register Description................................................................................................................. 103 19. 16-bit Timer/Counter1........................................................
23. USART - Universal Synchronous and Asynchronous serial Receiver and Transmitter.............................................................................................................190 23.1. Features................................................................................................................................... 190 23.2. Overview...................................................................................................................................190 23.3.
27.8. Using the JTAG Programming Capabilities.............................................................................. 286 27.9. Bibliography..............................................................................................................................287 27.10. IEEE 1149.1 (JTAG) Boundary-scan........................................................................................287 27.11. Data Registers....................................................................................
31.7. Pin Driver Strength................................................................................................................... 381 31.8. Pin Thresholds and Hysteresis.................................................................................................383 31.9. BOD Thresholds and Analog Comparator Offset..................................................................... 386 31.10. Internal Oscillator Speed............................................................................
1. Description The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
2. Configuration Summary Features ATmega32A Pin count 44 Flash (KB) 32 SRAM (KB) 2 EEPROM (KB) 1 General Purpose I/O pins 32 SPI 1 TWI (I2C) 1 USART 1 ADC 10-bit, up to 76.9ksps (15ksps at max resolution) ADC channels 8 AC propagation delay Typ 400ns 8-bit Timer/Counters 2 16-bit Timer/Counters 1 PWM channels 4 RC Oscillator +/-3% VREF Bandgap Operating voltage 2.7 - 5.
3. Ordering Information Speed (MHz) 16 Power Supply 2.7 - 5.5V Ordering Code(2) Package(1) ATmega32A-AU ATmega32A-AUR(3) 44A 44A ATmega32A-PU 40P6 ATmega32A-MU 44M1 ATmega32A-MUR(3) 44M1 ATmega32A-AN ATmega32A-ANR(3) 44A 44A ATmega32A-MN 44M1 ATmega32A-MNR(3) 44M1 Operational Range Industrial (-40oC to 85oC) Extended (-40oC to 105oC)(4) Note: 1. This device can also be supplied in wafer form.
4. Block Diagram Figure 4-1. Block Diagram SRAM TCK TMS TDI TDO JTAG OCD PARPROG MOSI MISO SCK CPU FLASH NVM programming EEPROMIF SPIPROG EEPROM Clock generation XTAL1 XTAL2 TOSC1 8MHz Crystal Osc 8MHz Calib RC 12MHz External RC Osc External clock 32.
Pin Configurations Figure 5-1.
Figure 5-2. Pinout PDIP ATmega32A AIN0/ INT2 5.1. VCC Digital supply voltage. 5.2. GND Ground. 5.3. PortA (PA7:PA0) Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.
Related Links System and Reset Characteristics on page 363 5.8. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 5.9. XTAL2 Output from the inverting Oscillator amplifier. 5.10. AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 5.11.
6. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
7. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
8. About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
9. Capacitive Touch Sensing The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most ® Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller.
10. AVR CPU Core 10.1. Overview This section discusses the Atmel AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 10-1.
as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
10.3.1. SREG – The AVR Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Bit 0 – C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 10.4. General Purpose Register File The Register File is optimized for the Atmel AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • • • • One 8-bit output operand and one 8-bit result input.
Figure 10-3. The X-, Y- and Z-Registers 15 X-re gis te r XH 7 XL 0 7 R27 (0x1B) 15 Y-re gis te r YL 0 Z-re gis te r ZH 7 0 0 7 R29 (0x1D) 15 0 R26 (0x1A) YH 7 0 0 R28 (0x1C) ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details). 10.5.
Figure 10-4. SPH and SPL – Stack Pointer High and Low Register Bit 15 14 13 12 11 10 9 8 0x3E S P15 S P14 S P13 S P12 S P11 S P10 S P9 S P8 S PH 0x3D S P7 S P6 S P5 S P4 S P3 S P2 S P1 S P0 S PL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Re a d/Write Initia l Va lue 0 0 Related Links SRAM Data Memory on page 30 10.6.
10.7. Reset and Interrupt Handling The Atmel AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<
11. AVR Memories 11.1. Overview This section describes the different memories in the Atmel AVR ATmega32A. The AVR architecture has two main memory spaces, the Data memory and the Program Memory space. In addition, the ATmega32A features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 11.2. In-System Reprogrammable Flash Program Memory The ATmega32A contains 32K bytes On-chip In-System Reprogrammable Flash memory for program storage.
11.3. SRAM Data Memory The figure below shows how the Atmel AVR ATmega32A SRAM Memory is organized. The lower 2144 Data memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 2048 locations address the internal data SRAM. The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
Figure 11-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCP U Addre s s Compute Addre s s Addre s s Va lid Write Da ta WR Re a d Da ta RD Me mory Vcce s s Ins truction 11.4. Next Ins truction EEPROM Data Memory The Atmel AVR ATmega32A contains 1Kbyte of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
11.4.2. EEPROM Write during Power-down Sleep Mode When entering Power-down sleep mode while an EEPROM write operation is active, the EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation is completed, the Oscillator continues running, and as a consequence, the device does not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down. 11.4.3.
11.6.1. EEARL – The EEPROM Address Register Low When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
11.6.2. EEARH – The EEPROM Address Register High When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
11.6.3. EEDR – The EEPROM Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
11.6.4. EECR – The EEPROM Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read.
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
12. 12.1. System Clock and Clock Options Clock Systems and their Distribution The figure below presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in Power Management and Sleep Modes. The clock systems are detailed in the following figure. Figure 12-1.
12.1.3. Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 12.1.4. Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 12.1.5.
12.3. Default Clock Source The device is shipped with CKSEL = “0001” and SUT = “10”. The default clock source setting is therefore the Internal RC Oscillator with longest startup time. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel Programmer. 12.4. Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in the figure below.
The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in the next table. Table 12-4. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1:0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) Recommended Usage 0 00 258 CK(1) 4.1ms Ceramic resonator, fast rising power 0 01 258 CK(1) 65ms Ceramic resonator, slowly rising power 0 10 1K CK(2) – Ceramic resonator, BOD enabled 0 11 1K CK(2) 4.
12.6. External RC Oscillator For timing insensitive applications, the external RC configuration shown in the figure below can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22pF. By programming the CKOPT Fuse, the user can enable an internal 36pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor. Figure 12-3.
The CKOPT Fuse should always be unprogrammed when using this clock option. During reset, hardware loads the 1MHz calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 5V, 25°C and 1.0MHz Oscillator frequency selected, this calibration gives a frequency within ± 3% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 1% accuracy at any given VCC and Temperature.
Figure 12-4. External Clock Drive Configuration EXTERNAL CLOCK S IGNAL When this clock source is selected, start-up times are determined by the SUT Fuses as shown in the following table. Table 12-10. Start-up Times for the External Clock Selection SUT1:0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) Recommended Usage 00 6 CK – BOD enabled 01 6 CK 4.
12.10.1. OSCCAL – The Oscillator Calibration Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
13. 13.1. Power Management and Sleep Modes Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. Figure Clock Distribution in section Clock Systems and their Distribution presents the different clock systems in the ATmega32A, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
13.2. Idle Mode When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
• If Timer/Counter2 is clocked asynchronously, i.e. the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK, and the global interrupt enable bit in SREG is set.
13.8.3. Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brownout Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Brown-out Detection for details on how to configure the Brown-out Detector. Related Links Brown-out Detection on page 56 13.8.4.
that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. 13.9.
13.9.1. MCUCR – MCU Control Register The MCU Control Register contains control bits for power management. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
14. System Control and Reset 14.1. Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 14-1. Reset Logic DATA BUS P ORF BORF EXTRF WDRF JTRF MCU Control a nd S ta tus Re gis te r (MCUCS R) Brown-Out Re s e t Circuit BODEN BODLEVEL P ull-up Re s is tor S P IKE FILTER JTAG Reset Register Wa tchdog Os cilla tor Clock Ge ne ra tor CK De lay Counte rs TIMEOUT CKS EL[3:0] S UT[1:0] Related Links IEEE 1149.1 (JTAG) Boundary-scan on page 287 14.2.1. Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit.
Figure 14-2. MCU Start-up, RESET Tied to VCC VCC RES ET VP OT VRS T tTOUT TIME-OUT INTERNAL RES ET Figure 14-3. Figure: MCU Start-up, RESET Extended Externally VCC VP OT RES ET TIME-OUT VRS T tTOUT INTERNAL RES ET Related Links System and Reset Characteristics on page 363 14.2.2. External Reset An External Reset is generated by a low level on the RESET pin.
14.2.3. Brown-out Detection ATmega32A has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
14.3. Internal Voltage Reference ATmega32A features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. 14.3.1. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in the table in System and Reset Characteristics.
Figure 14-7. Watchdog Timer WATCHDOG OS CILLATOR Related Links Watchdog Reset on page 56 14.5.
14.5.1. MCUCSR – MCU Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
14.5.2. WDTCR – Watchdog Timer Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
15. Interrupts This section describes the specifics of the interrupt handling performed by the ATmega32A. For a general explanation of the AVR interrupt handling, refer to Reset and Interrupt Handling. Related Links Reset and Interrupt Handling on page 27 15.1. Interrupt Vectors in ATmega32A Table 15-1. Reset and Interrupt Vectors Vector No.
2. When the IVSEL bit in GICR is set, interrupt vectors will be moved to the start of the Boot Flash section. The address of each interrupt vector will then be address in this table added to the start address of the boot Flash section. The next table shows Reset and interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations.
address Labels Code Comments $018 jmp SPI_STC ; SPI Transfer Complete Handler $01A jmp USART_RXC ; USART RX Complete Handler $01C jmp USART0_UDRE ; UDR Empty Handler $01E jmp USART0_TXC ; USART TX Complete Handler $020 jmp ADC ; ADC Conversion Complete Handler $022 jmp EE_RDY ; EEPROM Ready Handler $024 jmp ANA_COMP ; Analog Comparator Handler $026 jmp TWI ; Two-wire Serial Interface Handler $028 jmp SPM_RDY ; Store Program Memory Ready Handler ldi r16,high(RAMEND)
Adddress Labels Code Comments $000 RESET: ldi r16,high(RAMEND) ; Main program start $001 out SPH,r16 ; Set stack pointer to top of RAM $0002 ldi r16,low(RAMEND) $0003 out SPL,r16 $0004 sei $0005 xxx $3802 jmp EXT_INT0 ; IRQ0 Handler $3804 jmp EXT_INT1 ; IRQ1 Handler ; Enable interrupts ; .org $3802 :. :..
Address Labels Code Comments $3804 sei ; Enable interrupts $3805 xxx When the BOOTRST fuse is programmed, the Boot section size set to 4K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org $3800 $3800 jmp RESET ; Reset handler $3802 jmp EXT_INT0 ; IRQ0 Handler $3804 jmp EXT_INT1 ; IRQ1 Handler :. :..
15.2.1. GICR – General Interrupt Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
C Code Example void Move_interrupts(void) { /* Enable change of Interrupt Vectors */ GICR = (1<
16. External Interrupts The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0:2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt).
16.1.1. MCUCR – MCU Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
16.1.2. MCUCSR – MCU Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
16.1.3. GICR – General Interrupt Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
16.1.4. GIFR – General Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17. I/O Ports 17.1. Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Electrical Characteristics on page 359 17.2. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. The following figure shows a functional description of one I/O-port pin, here generically called Pxn. Figure 17-2.
PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem.
tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1-½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in the figure below. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 17-4.
Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 17.2.3. Digital Input Enable and Sleep Modes As shown in figure Figure 17-2, the digital input signal can be clamped to ground at the input of the Schmitt Trigger.
Figure 17-5.
Signal Name Full Name Description DDOE Data Direction Override Enable If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. DDOV Data Direction Override Value If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.
The two tables below relates the alternate functions of Port A to the overriding signals shown in the figure in section Alternate Port Functions. Table 17-4. Overriding Signals for Alternate Functions in PA7:PA4 Signal Name PA7/ADC7 PA6/ADC6 PA5/ADC5 PA4/ADC4 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO ADC7 INPUT ADC6 INPUT ADC5 INPUT ADC4 INPUT Table 17-5.
Port Pin Alternate Functions PB3 AIN1 (Analog Comparator Negative Input) OC0 (Timer/Counter0 Output Compare Match Output) PB2 AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt 2 Input) PB1 T1 (Timer/Counter1 External Counter Input) PB0 T0 (Timer/Counter0 External Counter Input) XCK (USART External Clock Input/Output) The alternate pin configuration is as follows: • SCK – Port B, Bit 7 SCK: Master Clock output, Slave Clock input pin for SPI.
T1, Timer/Counter1 Counter Source. • T0/XCK – Port B, Bit 0 T0, Timer/Counter0 Counter Source. XCK, USART External Clock. The Data Direction Register (DDB0) controls whether the clock is output (DDB0 set) or input (DDB0 cleared). The XCK pin is active only when the USART operates in Synchronous mode. The tables below relate the alternate functions of Port B to the overriding signals shown in the figure in section Alternate Port Functions.
17.3.3. Alternate Functions of Port C The Port C pins with alternate functions are shown in the table below. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. Table 17-9.
SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the Twowire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation.
Signal Name PC3/TMS PC2/TCK PC1/SDA PC0/SCL DIEOV 0 0 0 0 DI – – – – AIO TMS TCK SDA INPUT SCL INPUT Note: 1. When enabled, the Two-wire Serial Interface enables slew-rate controls on the output pins PC0 and PC1. This is not shown in the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. 17.3.4.
INT1, External Interrupt Source 1: The PD3 pin can serve as an external interrupt source. • INT0 – Port D, Bit 2 INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt source. •TXD – Port D, Bit 1 TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1. • RXD – Port D, Bit 0 RXD, Receive Data (Data input pin for the USART).
Signal Name PD3/INT3/TXD1 PD2/INT2/RXD1 PD1/INT1/SDA PD0/INT0/SCL DIEOV 1 1 0 0 DI INT1 INPUT INT0 INPUT – RXD AIO – – – – 17.4.
17.4.1. SFIOR – Special Function IO Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17.4.2. PORTA – Port A Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17.4.3. DDRA – Port A Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17.4.4. PINA – Port A Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17.4.5. PORTB – The Port B Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17.4.6. DDRB – The Port B Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17.4.7. PINB – The Port B Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17.4.8. PORTC – The Port C Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17.4.9. DDRC – The Port C Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17.4.10. PINC – The Port C Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. In ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being Push-Pull Zero Output. The port pins assumes their initial value, even if the clock is not running.
17.4.11. PORTD – The Port D Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17.4.12. DDRD – The Port D Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
17.4.13. PIND – The Port D Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
18. Timer/Counter0 and Timer/Counter1 Prescalers 18.1. Overview Timer/Counte1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to Timer/Counte1 and Timer/Counter0. 18.2. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling.
18.5.1. SFIOR – Special Function IO Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
19. 16-bit Timer/Counter1 19.1. Features • • • • • • • • • • • 19.2. True 16-bit Design (i.e.
Figure 19-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA TCCRnB Note: 1.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICPn) or on the Analog Comparator pins (see Analog Comparator). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values.
16-bit read or write operation. When the Low byte of a 16-bit register is written by the CPU, the High byte stored in the temporary register, and the Low byte written are both copied into the 16-bit register in the same clock cycle. When the Low byte of a 16-bit register is read by the CPU, the High byte of the 16-bit register is copied into the temporary register in the same clock cycle as the Low byte is read. Not all 16-bit accesses uses the temporary register for the High byte.
C Code Example(1) unsigned int TIM16_ReadTCNTn( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNTn into i */ i = TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. See About Code Examples. The assembly code example returns the TCNTn value in the r17:r16 Register pair. The following code examples show how to do an atomic write of the TCNTn Register contents.
19.4. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CSn2:0) bits located in the Timer/Counter Control Register B (TCCRnB). For details on clock sources and prescaler, see Timer/ Counte1 and Timer/Counter0 Prescalers. Related Links Timer/Counter0 and Timer/Counter1 Prescalers on page 102 19.5.
the TCNTn value can be accessed by the CPU, independent of whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare Outputs OCnx.
Input Capture interrupt. The ICFn Flag is automatically cleared when the interrupt is executed. Alternatively the ICFn Flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the Low byte (ICRnL) and then the High byte (ICRnH). When the Low byte is read the High byte is copied into the High byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location).
Figure 19-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator WGMn3:0 OCnx COMnx1:0 The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes.
19.7.2. Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. 19.7.3.
The general I/O port function is overridden by the Output Compare (OCnx) from the waveform generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions.
19.9.2. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency.
PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA.
is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA.
In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown in the figure below.
on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at Compare Match between OCRnx and TCNTn when the counter decrements.
Figure 19-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx[1:0] = 0x2) OCnx (COMnx[1:0] = 0x3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM).
If OCRnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle. 19.10. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering).
Figure 19-12. Timer/Counter Timing Diagram, no Prescaling. clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM TOP - 1 TOP TOP - 1 BOTTOM + 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) New OCRnx Value Old OCRnx Value The next figure shows the same timing data, but with the prescaler enabled. Figure 19-13.
19.11.1. TCCR1A – Timer/Counter1 Control Register A When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Table 19-3. Compare Output Mode, Fast PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM (non-inverting mode) 1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM (inverting mode) Note: 1.
Bits 1:0 – WGM1n: Waveform Generation Mode [n = 1:0] Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, refer to the table below. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See Modes of Operation). Table 19-5.
19.11.2. TCCR1B – Timer/Counter1 Control Register B When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
CA12 CA11 CS10 Description 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output.
19.11.3. TCNT1L – Timer/Counter1 Low byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
19.11.4. TCNT1H – Timer/Counter1 High byte Name: TCNT1H Offset: 0x2D Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x4D Bit 7 6 5 4 3 2 1 0 TCNT1H[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TCNT1H[7:0]: Timer/Counter 1 High byte Refer to TCNT1L.
19.11.5. OCR1AL – Output Compare Register 1 A Low byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
19.11.6. OCR1AH – Output Compare Register 1 A High byte Name: OCR1AH Offset: 0x2B Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x4B Bit 7 6 5 4 3 2 1 0 OCR1AH[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR1AH[7:0]: Output Compare 1 A High byte Refer to OCR1AL.
19.11.7. OCR1BL – Output Compare Register 1 B Low byte Name: OCR1BL Offset: 0x28 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x48 Bit 7 6 5 4 3 2 1 0 OCR1BL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR1BL[7:0]: Output Compare 1 B Low byte Refer to OCR1AL.
19.11.8. OCR1BH – Output Compare Register 1 B High byte Name: OCR1BH Offset: 0x29 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x49 Bit 7 6 5 4 3 2 1 0 OCR1BH[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR1BH[7:0]: Output Compare 1 B High byte Refer to OCR1AL.
19.11.9. ICR1L – Input Capture Register 1 Low byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
19.11.10. ICR1H – Input Capture Register 1 High byte Name: ICR1H Offset: 0x27 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x47 Bit 7 6 5 4 3 2 1 0 ICR1H[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – ICR1H[7:0]: Input Capture 1 High byte Refer to ICR1L.
19.11.11. TIMSK – Timer/Counter Interrupt Mask Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.
19.11.12. TIFR – Timer/Counter Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.
20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 20.1. Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) • Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
20.2.1. Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units.
Figure 20-2. Counter Unit Block Diagram TOVn (Int. Re q.) DATA BUS TOS C1 count TCNTn cle a r Control Logic clk Tn T/C Os cilla tor P re s ca le r dire ction BOTTOM TOS C2 TOP clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkT2 Timer/Counter clock. TOP Signalizes that TCNT2 has reached maximum value.
Figure 20-3. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Compa ra tor ) OCFn (Int. Re q.) TOP BOTTOM Wave form Ge ne ra tor OCxy FOCn WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence.
Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even when changing between waveform generation modes.
The design of the Output Compare Pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See Register Description. 20.6.1. Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2 Register is to be performed on the next Compare Match.
Figure 20-5. CTC Mode, Timing Diagram OCn Inte rrupt Fla g S e t TCNTn OCn (Toggle ) Pe riod (COMn1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 20-6. Fast PWM Mode, Timing Diagram OCRn Inte rrupt Fla g S e t OCRn Upda te a nd TOVn Inte rrupt Fla g S e t TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Pe riod 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2 while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits.
continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in the timing diagram above OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match: • OCR2A changes its value from MAX, like in the timing diagram above.
Figure 20-10. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Va lue OCFn The figure below shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 20-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) OCRn TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCFn 20.9.
6. Enable interrupts, if needed. • The Oscillator is optimized for use with a 32.768kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1.
1. 2. 3. Write any value to either of the registers OCR2 or TCCR2. Wait for the corresponding Update Busy Flag to be cleared. Read TCNT2. • During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag.
20.11.1. TCCR2 – Timer/Counter Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. The following table shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). Table 20-3. Compare Output Mode, Non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected.
Bits 2:0 – CS2n: Clock Select [n = 2:0] The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 20-6. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped).
20.11.2. TCNT0 – Timer/Counter Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock.
20.11.3. OCR0 – Output Compare Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0 pin.
20.11.4. ASSR – Asynchronous Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
20.11.5. TIMSK – Timer/Counter Interrupt Mask Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
20.11.6. TIFR – Timer/Counter Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
20.11.7. SFIOR – Special Function IO Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
21. 8-bit Timer/Counter0 with PWM 21.1. Features • • • • • • • Overview Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in the figure below. For the actual placement of I/O pins, refer to Pin Configurations. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Register Description. Figure 21-1.
21.2.1. Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units.
Figure 21-2. Counter Unit Block Diagram TOVn (Int. Re q.) DATA BUS Clock Select Edge Detector count TCNTn cle a r Control Logic Tn dire ction (From Prescaler) BOTTOM TOP Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Selects between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkT0 Timer/Counter clock. TOP Signalizes that TCNT0 has reached maximum value. BOTTOM Signalizes that TCNT0 has reached minimum value (zero).
Figure 21-3. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Compa ra tor ) OCFn (Int. Re q.) TOP BOTTOM Wave form Ge ne ra tor OCn FOCn WGMn1:0 COMn1:0 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence.
21.6. Compare Match Output Unit The Compare Output mode (COM01:0) bits have two functions. The waveform generator uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match. Also, the COM01:0 bits control the OC0 pin output source. The figure below shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
21.7. Modes of Operation The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM01:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
If the new value written to OCR0 is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM01:0 = 1).
Figure 21-6. Fast PWM Mode, Timing Diagram OCRn Inte rrupt Fla g S e t OCRn Upda te a nd TOVn Inte rrupt Fla g S e t TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Pe riod 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin.
operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction.
At the very start of period 2 in the timing diagram OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without a Compare Match: • OCR0 changes its value from MAX, like in the timing diagram above. When the OCR0 value is MAX the OCn pin value is the same as the result of a down-counting Compare Match.
Figure 21-10. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Va lue OCFn The next figure shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. Figure 21-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) OCRn TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCFn 21.9.
21.9.1. TCCR0 – Timer/Counter Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
the Data Direction Register (DDR) bit corresponding to the OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. The following table shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 21-3. Compare Output Mode, Non-PWM Mode COM01 COM00 Description 0 0 Normal port operation, OC0 disconnected.
Bits 2:0 – CS0n: Clock Select [n = 2:0] The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 21-6. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge.
21.9.2. TCNT0 – Timer/Counter Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock.
21.9.3. OCR0 – Output Compare Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0 pin.
21.9.4. TIMSK – Timer/Counter Interrupt Mask Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
21.9.5. TIFR – Timer/Counter Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
22. SPI – Serial Peripheral Interface 22.1. Features Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • • • • End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega32A and peripheral devices or between several AVR devices.
The interconnection between Master and Slave CPUs with SPI is shown in the figure below. The system consists of two shift registers, and a Master Clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
Table 22-1. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. Refer to table Port B Pins Alternate Functions in Alternate Functions of Port B for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
Assembly Code Example(1) SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<
If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the pin will be driving the SS pin of the SPI Slave. If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it.
Figure 22-4. SPI Transfer Format with CPHA = 1 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) 22.5.
22.5.1. SPCR – SPI Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Table 22-4. CPHA Functionality CPHA Leading Edge Trailing Edge 0 Sample Setup 1 Setup Sample Bits 1:0 – SPRn: SPI Clock Rate Select [n = 1:0] These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the table below. Table 22-5.
22.5.2. SPSR – SPI Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
22.5.3. SPDR – SPI Data Register is a read/write register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
23. USART - Universal Synchronous and Asynchronous serial Receiver and Transmitter 23.1. Features • • • • • • • • • • • • 23.2.
Figure 23-1. USART Block Diagram(1) Clock Generator UBRRn [H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCKn Transmitter TX CONTROL DATA BUS UDRn(Transmit) PARITY GENERATOR PIN CONTROL TRANSMIT SHIFT REGISTER TxDn Receiver CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDRn (Receive) PARITY CHECKER UCSRnA UCSRnB RxDn UCSRnC Note: 1.
23.2.1. AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • • • • • Bit locations inside all USART Registers. Baud Rate Generation. Transmitter Operation. Transmit Buffer Functionality. Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer.
Figure 23-2. Clock Generation Logic, Block Diagram UBRRn U2Xn foscn Prescaling Down-Counter UBRRn+1 /2 /4 /2 0 1 0 OSC DDR_XCKn xcki XCKn Pin Sync Register Edge Detector xcko DDR_XCKn 1 0 UMSELn 1 UCPOLn txclk 1 0 rxclk Signal description: 23.3.1. txclk Transmitter clock (internal signal). rxclk Receiver base clock (internal signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (internal signal).
Table 23-1. Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal mode (U2X = 0) Asynchronous Double Speed mode (U2X = 1) Synchronous Master mode Equation for Calculating Baud Rate(1) BAUD = BAUD = BAUD = Equation for Calculating UBRR Value �OSC 16 ���� + 1 ���� = �OSC 2 ����+1 ���� = �OSC 8 ���� + 1 ���� = �OSC −1 16BAUD �OSC −1 8BAUD �OSC −1 2BAUD Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).
Figure 23-3. Synchronous Mode XCK Timing UCPOL = 1 XCK RxD / TxD Sample UCPOL = 0 XCK RxD / TxD Sample The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As the figure above shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. 23.4.
The USART Character Size (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop bit is zero 23.4.1. Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits.
#define MYUBRR FOSC/16/BAUD-1 void main( void ) { ... USART_Init(MYUBRR) ... } void USART_Init( unsigned int ubrr) { /*Set baud rate */ UBRR0H = (unsigned char)(ubrr>>8); UBRR0L = (unsigned char)ubrr; Enable receiver and transmitter */ UCSRB = (1<
C Code Example(1) void USART_Transmit( unsigned char data ) { /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<
23.6.3. Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts. The Data Register Empty (UDRE) Flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register.
The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDR will be masked to zero. The USART has to be initialized before the function can be used.
C Code Example(1) unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* Wait for data to be received */ while ( !(UCSRA & (1<> 1) & 0x01; return ((resh << 8) | resl); } Note: 1. See About Code Examples.
The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DOR Flag is set there was one or more serial frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA.
23.8. Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver.
having the sample number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels, the received bit is registered to be a logic 1. If two or all three samples have low levels, the received bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit.
Table 23-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D Rslow [%] Rfast [%] Max. Total Error [%] Recommended Max Receiver Error # (Data+Parity Bit) [%] 5 93.20 106.67 +6.67/-6.8 ±3.0 6 94.12 105.79 +5.79/-5.88 ±2.5 7 94.81 105.11 +5.11/-5.19 ±2.0 8 95.36 104.58 +4.58/-4.54 ±2.0 9 95.81 104.14 +4.14/-4.19 ±1.5 10 96.17 103.78 +3.78/-3.83 ±1.5 Table 23-3.
first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several Slave MCUs to receive data from a Master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
ldi r16,(1<
About Code Examples on page 19 23.11.
23.11.1. UDR – USART I/O Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
23.11.2. UCSRA – USART Control and Status Register A When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. Bit 0 – MPCM: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode.
23.11.3. UCSRB – USART Control and Status Register B When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Bit 0 – TXB8: Transmit Data Bit 8 TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR.
23.11.4. UCSRC – USART Control and Status Register C When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The UCSRC Register shares the same I/O location as the UBRRH Register. See the Accessing UBRRH/ UCSRC Registers section which describes how to access this register.
Table 23-6. USBS Bit Settings USBS Stop Bit(s) 0 1-bit 1 2-bit Bits 2:1 – UCSZn: Character Size [n = 1:0] The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use. Table 23-7.
23.11.5. UBRRL – USART Baud Rate Register Low When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
23.11.6. UBBRH – USART Baud Rate Register High When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The UBRRH Register shares the same I/O location as the UCSRC Register. See the Accessing UBRRH/ UCSRC Registers section which describes how to access this register.
Baud Rate [bps] fosc = 1.0000MHz U2X = 0 fosc = 1.8432MHz U2X = 1 U2X= 0 fosc = 2.0000MHz U2X = 1 U2X = 0 U2X = 1 UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.
Table 23-11. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) Baud Rate [bps] fosc = 8.0000MHz U2X = 0 U2X = 1 UBRR Error UBRR Error 2400 207 0.2% 416 4800 103 0.2% 9600 51 0.2% 14.4k 34 19.2k fosc = 11.0592MHz fosc = 14.7456MHz U2X = 0 U2X = 0 U2X = 1 Error UBRR Error UBRR Error UBRR Error -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.
Baud Rate [bps] fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz U2X = 0 U2X = 0 U2X = 0 U2X = 1 UBRR Error 115.2k 8 230.4k UBRR U2X = 1 U2X = 1 Error UBRR Error UBRR Error UBRR Error -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4% 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5M 1 0.0% 3 0.0% – – 4 -7.8% – – 4 0.0% 1M 0 0.0% 1 0.0% – – – – – – – Max.(1) 1Mbps 2Mbps 1.
24. TWI - Two-wire Serial Interface 24.1. Features • • • • • • • • • • Overview The TWI module is comprised of several submodules, as shown in the following figure. All registers drawn in a thick line are accessible through the AVR data bus. Figure 24-1.
24.2.1. SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slewrate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section.
and wakes up the CPU, the TWI aborts operation and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the only enabled interrupt when entering Power-down. 24.2.5. Control Unit The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted.
Table 24-1. TWI Terminology 24.3.2. Term Description Master The device that initiates and terminates a transmission. The Master also generates the SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus. Electrical Interconnection As depicted in Figure 24-2, both bus lines are connected to the positive supply voltage through pull-up resistors.
and STOP condition. This is referred to as a REPEATED START condition, and is used when the Master wishes to initiate a new transfer without relinquishing control of the bus. After a REPEATED START, the bus is considered busy until the next STOP. This is identical to the START behavior, and therefore START is used to describe both START and REPEATED START for the remainder of this datasheet, unless otherwise noted.
24.4.4. Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled.
24.5. Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • • An algorithm must be implemented allowing only one of the masters to complete the transmission.
Figure 24-9. Arbitration Between Two Masters START SD A from Master A Master A Loses Arbitration, SD AA SDA SD A from Master B SD A Line Synchroniz ed SCL Line Note that arbitration is not allowed between: • • • A REPEATED START condition and a data bit. A STOP condition and a data bit. A REPEATED START and a STOP condition. It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
Application Action Figure 24-10. Interfacing the Application to the TWI in a Typical Transmission 1. Application writes to TWCRto initiate transmission of START TWI Hardware Action TWI bus 1. 2. 3. 4. 5. 6. 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one, and TWSTA is written to zero. START 2.TWINT set. Status code indicates START condition sent SLA+W 5.
7. The application software should now examine the value of TWSR, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a STOP condition. Which value to write is described later on.
Assembly Code Example 24.6.1. Comments Wait for TWINT Flag set. This indicates wait3: in r16,TWCR sbrs r16,TWINT rjmp wait3 while (!(TWCR & (1<
24.6.2. Master Transmitter Mode In the Master Transmitter (MT) mode, a number of data bytes are transmitted to a Slave Receiver, see figure below. In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether MT or Master Receiver (MR) mode is to be entered: If SLA +W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 24-3.
Figure 24-12.
Figure 24-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........ Device n R1 R2 SD A SCL A START condition is sent by writing to the TWI Control register (TWCR) a value of the type TWCR=1x10x10x: • TWCR.TWEN must be written to '1' to enable the 2-wire Serial Interface • TWCR.TWSTA must be written to '1' to transmit a START condition • TWCR.TWINT must be cleared by writing a '1' to it.
Table 24-4.
Figure 24-14. Formats and States in the Master Receiver Mode MR Successfull reception from a sla v e receiv er S SLA $08 R A DATA $40 A DATA $50 A P $58 Next transf er star ted with a repeated star t condition RS SLA R $10 Not ac kno wledge received after the slave address A W P $48 Arbitration lost in sla ve address or data b yte MT A or A Other master contin ues A $38 Arbitration lost and addressed as sla ve A $68 From master to sla ve From slave to master 24.6.4.
Figure 24-15. Data transfer in Slave Receiver mode VCC Device 1 Device 2 SLAVE RECEIVER MASTER TRANSMITTER Device 3 ........ Device n R1 R2 SD A SCL To initiate the SR mode, the TWI (Slave) Address Register (TWAR) and the TWI Control Register (TWCR) must be initialized as follows: The upper seven bits of TWAR are the address to which the 2-wire Serial Interface will respond when addressed by a Master (TWAR.TWA[6:0]). If the LSB of TWAR is written to TWAR.
Table 24-5.
Status Code (TWSR) Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWDR 0x98 To TWCR STA Prescaler Bits are 0 Next Action Taken by TWI Hardware STO TWI NT TWE A Previously addressed with general call; data has been Read data byte or 0 Read data byte or 0 0 0 1 1 0 1 Switched to the not addressed Slave mode; no recognition of own SLA or GCA received; NOT ACK has been Read data byte or 1 0 1 0 Switched to the not addressed Slave m
Figure 24-16. Formats and States in the Slave Receiver Mode Reception of the o wn sla ve address and one or more data b ytes.
Figure 24-17. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 SLAVE TRANSMITTER MASTER RECEIVER Device 3 ........ Device n R1 R2 SD A SCL To initiate the SR mode, the TWI (Slave) Address Register (TWAR) and the TWI Control Register (TWCR) must be initialized as follows: The upper seven bits of TWAR are the address to which the 2-wire Serial Interface will respond when addressed by a Master (TWAR.TWA[6:0]). If the LSB of TWAR is written to TWAR.
Table 24-6.
Figure 24-18. Formats and States in the Slave Transmitter Mode Reception of the o wn sla ve address and one or more data b ytes S SLA R A DATA A $A8 Arbitration lost as master and addressed as sla ve DATA $B8 A P or S $C0 A $B0 Last data b yte tr ansmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S $C8 DATA From master to sla ve From slave to master 24.6.6.
1. 2. 3. 4. The transfer must be initiated. The EEPROM must be instructed what location should be read. The reading must be performed. The transfer must be finished. Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed.
• • Two or more masters are accessing the same Slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a '1' on SDA while another Master outputs a zero will lose the arbitration. Losing masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. Two or more masters are accessing different slaves.
24.8.1. TWBR – TWI Bit Rate Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
24.8.2. TWCR – TWI Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The TWCR is used to control the operation of the TWI.
Bit 4 – TWSTO: TWI STOP Condition Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state.
24.8.3. TWSR – TWI Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
24.8.4. TWDR – TWI Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware.
24.8.5. TWAR – TWI (Slave) Address Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes.
25. AC - Analog Comparator 25.1. Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
25.3.
25.3.1. SFIOR – Analog Comparator Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
25.3.2. ACSR – Analog Comparator Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Table 25-2. ACIS[1:0] Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.
26. ADC - Analog to Digital Converter 26.1. Features • • • • • • • • • • • • • • • • 26.2. 10-bit Resolution 0.5 LSB Integral Non-Linearity ±2 LSB Absolute Accuracy 13 - 260μs Conversion Time Up to 15ksps at Maximum Resolution 8 Multiplexed Single Ended Input Channels 7 Differential Input Channels 2 Differential Input Channels with Optional Gain of 10x and 200x Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 2.7 - VCC Differential ADC Voltage Range Selectable 2.
Figure 26-1. Analog to Digital Converter Block Schematic Operation ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS0 ADPS1 ADPS2 ADIF ADATE ADEN ADSC MUX1 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. Prescaling and Conversion Timing Figure 26-3. ADC Prescaler ADEN START Reset CK/64 CK/128 CK/32 CK/8 CK/16 CK/4 7-BIT ADC PRESCALER CK CK/2 26.4.
Figure 26-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion Cycle Number 1 12 2 13 14 16 15 17 18 19 20 21 23 22 24 25 1 2 3 ADC Clock ADEN ADSC ADIF Sign and MSB of Result ADCH LSB of Result ADCL MUX and REFS Update Conversion Complete Sample and Hold MUX and REFS Update Figure 26-5.
Figure 26-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Conversion Complete Sample and Hold MUX and REFS Update Table 26-1. ADC Conversion Time 26.4.1. Condition Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 Auto Triggered conversions 2 13.
(writing ADEN in ADCSRA to “0” then to “1”), only extended conversions are performed. The result from the extended conversions will be valid. Refer to Prescaling and Conversion Timing for timing details. 26.5. Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion.
26.5.2. ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.56V reference, or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the internal bandgap reference (VBG) through an internal amplifier.
sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedance sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. If differential gain channels are used, the input circuitry looks somewhat different, although source impedances of a few hundred kΩ or less is recommended.
Analog Ground Plane PA3 (ADC3) PA2 (ADC2) PA1 (ADC1) PA0 (ADC0) VCC GND Figure 26-9. ADC Power Connections PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) AREF 10μH PA7 (ADC7) AVCC 100nF GND PC7 26.6.3. Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs.
Figure 26-10. Offset Error Output Code Ideal ADC Actual ADC Offset Error • VREF Input Voltage Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB. Figure 26-11.
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 26-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 • • 26.7. VREF Input Voltage Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
Figure 26-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF /GAIN 0 0x3FF VREF /GAIN Diffe re ntia l Input Volta ge (Volts ) 0x200 Table 26-2. Correlation Between Input Voltage and Output Codes VADCn Read Code Corresponding decimal value VADCm + VREF /GAIN 0x1FF 511 VADCm + 511/512 VREF /GAIN 0x1FF 511 VADCm + 510/512 VREF /GAIN 0x1FE 510 :. :. :. VADCm + 1/512 VREF /GAIN 0x001 1 VADCm 0x000 0 VADCm - 1/512 VREF /GAIN 0x3FF -1 :. :. :.
Voltage on ADC3 is 300mV, voltage on ADC2 is 500mV. ADCR = 512 × 10 × (300 - 500) / 2560 = -400 = 0x270 ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. 26.8.
26.8.1. ADMUX – ADC Multiplexer Selection Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Table 26-4.
MUX[4:0] Single Ended Input 11110 1.22V (VBG) 11111 0V (GND) Positive Differential Input Negative Differential Input Gain N/A Note: 1. Can be used for offset calibration.
26.8.2. ADCSRA – ADC Control and Status Register A When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Table 26-5.
26.8.3. ADCL – ADC Data Register Low (ADLAR=0) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. When ADCL is read, the ADC Data Register is not updated until ADCH is read.
26.8.4. ADCH – ADC Data Register High (ADLAR=0) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
26.8.5. ADCL – ADC Data Register Low (ADLAR=1) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
26.8.6. ADCH – ADC Data Register High (ADLAR=1) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
26.8.7. SFIOR – Special Function IO Register Name: SFIOR Offset: 0x30 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x50 Bit Access Reset 7 6 5 ADTS2 ADTS1 ADTS0 R/W R/W R/W 0 0 0 4 3 2 1 0 Bits 7:5 – ADTSn: ADC Auto Trigger Source [n = 2:0] If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect.
27. JTAG Interface and On-chip Debug System 27.1. Features • • • • • • 27.2. JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the IEEE std. 1149.
TAP – Test Access Port The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are: • • • • TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine. TCK: Test clock. JTAG operation is synchronous to TCK. TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). TDO: Test Data Out.
Figure 27-2. TAP Controller State Diagram 1 Te s t-Logic-Re s e t 0 0 Run-Te s t/Idle 1 S e le ct-DR S ca n 1 S e le ct-IR S ca n 0 0 1 1 Ca pture -DR Ca pture -IR 0 0 S hift-DR S hift-IR 0 1 Exit1-DR 0 P a us e -DR 0 0 P a us e -IR 1 1 0 Exit2-DR Exit2-IR 1 1 Upda te -DR 27.4.
• • • held low during input of the 3 LSBs in order to remain in the Shift-IR state. The MSB of the instruction is shifted in when this state is left by setting TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state.
• • 2 Single Program Memory break points + 1 Program Memory break point with mask (“range break point”) 2 Single Program Memory break points + 1 Data Memory break point with mask (“range break point”) A debugger, like the Atmel Studio®, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in On-chip Debug Specific JTAG Instructions.
The JTAG programming capability supports: • • • • Flash programming and verifying EEPROM programming and verifying Fuse programming and verifying Lock bit programming and verifying The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no back-door exists for reading out the content of a secured device.
the BYPASS instruction can be issued to make the shortest possible scan chain through the device. The device can be set in the Reset state either by pulling the external RESET pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register. The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR-register.
Table 27-1. AVR JTAG Part Number Part Number JTAG Part Number (Hex) ATmega32A 0x9502 27.11.2.3. Manufacturer ID The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is listed in the table below. Table 27-2. Manufacturer ID Manufacturer JTAG Manufacturer ID (Hex) ATMEL 0x01F 27.11.3. Reset Register The Reset Register is a Test Data Register used to reset the part.
27.12. Boundry-scan Specific JTAG Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not implemented, but all outputs with tri-state capability can be set in high-impedant state by using the AVR_RESET instruction, since the initial state for all port pins is tri-state.
• Shift-DR: The Reset Register is shifted by the TCK input. 27.12.5. BYPASS; 0xF Mandatory JTAG instruction selecting the Bypass Register for Data Register. The active states are: • • Capture-DR: Loads a logic “0” into the Bypass Register. Shift-DR: The Bypass Register cell between TDI and TDO is shifted. 27.13.
Figure 27-5. Boundary-scan Cell for Bi-directional Port Pin with Pull-Up Function.
Figure 27-6.
Figure 27-7. Additional Scan Signal for the Two-wire Interface PUExn OCxn ODxn Pxn TWIEN SRC Slew-rate limited IDxn 27.13.3. Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard Reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in the figure below is inserted both for the 5V Reset signal; RSTT, and the 12V Reset signal; RSTHV. Figure 27-8.
The figure below shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general boundary-scan cell, while the Oscillator/Clock output is attached to an observe-only cell. In addition to the main clock, the Timer Oscillator is scanned in the same way. The output from the internal RC Oscillator is not scanned, as this Oscillator does not have external connections. Figure 27-9.
chain, so the boundary scan chain can not make a XTAL Oscillator requiring internal capacitors to run unless the fuse is correctly programmed. 27.13.5. Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in the first figure below. The Boundary-scan cell from the second figure below is attached to each of these signals. The signals are described in Table 27-4.
Table 27-4.
Table 27-5.
Signal Name Direction as Description Seen from the ADC Recommended Input when not in Use Output Values when Recommended Inputs are Used, and CPU is not Using the ADC HOLD Input Sample & Hold signal. Sample 1 analog signal when low. Hold signal when high. If gain stages are used, this signal must go active when ACLK is high.
Signal Name Direction as Description Seen from the ADC Recommended Input when not in Use Output Values when Recommended Inputs are Used, and CPU is not Using the ADC ST Input Output of gain stages will settle faster if this signal is high first two ACLK periods after AMPEN goes high. 0 0 VCCREN Input Selects Vcc as the ACC reference voltage. 0 0 Note: 1. Incorrect setting of the switches in Figure 27-12 will make signal contention and may damage the part.
columns. The verification should be done on the data scanned out when scanning in the data on the same row in the table. Table 27-6.
Table 27-7.
Bit Number Signal Name Module 111 MUXEN_6 ADC 110 MUXEN_5 109 MUXEN_4 108 MUXEN_3 107 MUXEN_2 106 MUXEN_1 105 MUXEN_0 104 NEGSEL_2 103 NEGSEL_1 102 NEGSEL_0 101 PASSEN 100 PRECH 99 SCTEST 98 ST 97 VCCREN Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 303
Bit Number Signal Name Module 96 PB0.Data Port B 95 PB0.Control 94 PB0.Pullup_Enable 93 PB1.Data 92 PB1.Control 91 PB1.Pullup_Enable 90 PB2.Data 89 PB2.Control 88 PB2.Pullup_Enable 87 PB3.Data 86 PB3.Control 85 PB3.Pullup_Enable 84 PB4.Data 83 PB4.Control 82 PB4.Pullup_Enable 81 PB5.Data 80 PB5.Control 79 PB5.Pullup_Enable 78 PB6.Data 77 PB6.Control 76 PB6.Pullup_Enable 75 PB7.Data 74 PB7.Control 73 PB7.
Bit Number Signal Name Module 66 EXTCLK (XTAL1) 65 OSCCK Clock input and Oscillators for the main clock (Observe-only) 64 RCCK 63 OSC32CK 62 TWIEN TWI 61 PD0.Data Port D 60 PD0.Control 59 PD0.Pullup_Enable 58 PD1.Data 57 PD1.Control 56 PD1.Pullup_Enable 55 PD2.Data 54 PD2.Control 53 PD2.Pullup_Enable 52 PD3.Data 51 PD3.Control 50 PD3.Pullup_Enable 49 PD4.Data 48 PD4.Control 47 PD4.Pullup_Enable 46 PD5.Data 45 PD5.Control 44 PD5.Pullup_Enable 43 PD6.
Bit Number Signal Name Module 37 PC0.Data Port C 36 PC0.Control 35 PC0.Pullup_Enable 34 PC1.Data 33 PC1.Control 32 PC1.Pullup_Enable 31 PC6.Data 30 PC6.Control 29 PC6.Pullup_Enable 28 PC7.Data 27 PC7.Control 26 PC7.
Bit Number Signal Name Module 23 PA7.Data Port A 22 PA7.Control 21 PA7.Pullup_Enable 20 PA6.Data 19 PA6.Control 18 PA6.Pullup_Enable 17 PA5.Data 16 PA5.Control 15 PA5.Pullup_Enable 14 PA4.Data 13 PA4.Control 12 PA4.Pullup_Enable 11 PA3.Data 10 PA3.Control 9 PA3.Pullup_Enable 8 PA2.Data 7 PA2.Control 6 PA2.Pullup_Enable 5 PA1.Data 4 PA1.Control 3 PA1.Pullup_Enable 2 PA0.Data 1 PA0.Control 0 PA0.Pullup_Enable Note: 1.
27.16.
27.16.1. OCDR – On-chip Debug Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
27.16.2. MCUCSR – MCU Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The MCU Control and Status Register contains control bits for general MCU functions, and provides information on which reset source caused an MCU Reset.
28. BTLDR - Boot Loader Support – Read-While-Write Self-Programming 28.1. Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 1. A page is a section in the Flash consisting of several bytes (see Table. No. of Words in a Page and No.
28.4. Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-Write (NRWW) section.
Figure 28-1. Read-While-Write vs.
Figure 28-2.
• • To protect only the Application Flash section from a software update by the MCU Allow software update in the entire Flash The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 1) does not control reading nor writing by LPM/SPM, if it is attempted.
once the Boot Reset Fuse is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 28-4. Boot Reset Fuse BOOTRST Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset, as described by the Boot Loader Parameters Note: '1' means unprogrammed, '0' means programmed. 28.7.
Figure 28-3. Addressing the Flash During SPM(1) BIT 15 ZPAGEMSB ZPCMSB 1 0 0 Z - REGISTER PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 1. Fo the different variables used in the figure, see the table of the different variables used and the Mapping to the Z-pointer in the boot loader parameters section. 2.
• • Fill temporary page buffer Perform a Page Write If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data.
Interrupts on page 62 28.8.5. Consideration While Updating Boot Loader Section (BLS) Special care must be taken if the user allows the Boot Loader Section (BLS) to be updated by leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further software updates might be impossible.
Bit 7 6 5 4 3 2 1 0 Rd – – – BLB12 – BLB11 – BLB02 – BLB01 LB2 LB1 The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock Bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse Low bits (FLB) will be loaded in the destination register as shown below.
28.8.12. Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during self-programming (page erase and page write).
rcall Do_spm ; read back and check, optional ldi looplo, low(PAGESIZEB) ;init loop variable ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 subi YL, low(PAGESIZEB) ;restore pointer sbci YH, high(PAGESIZEB) Rdloop: lpm r0, Z+ ld r1, Y+ cpse r0, r1 rjmp Error sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256 brne Rdloop ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable
sbic EECR, EEWE rjmp Wait_ee ; SPM timed sequence out SPMCR, spmcrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret 28.8.13. ATmega32A Boot Loader Parameters In the following tables, the parameters used in the description of the self programming are given. Table 28-6.
Table 28-8. Explanation of Different Variables used in figure "Addressing the Flash During SPM" from earlier in this chapter and the Mapping to the Z-pointer, ATmega32A Variable Corresponding Zvalue(1) Description PCMSB 13 Most significant bit in the Program Counter. (The Program Counter is 14 bits PC[13:0]) PAGEMSB 5 Most significant bit which is used to address the words within one page (64 words in a page requires 6 bits PC [5:0]). ZPCMSB Z14 Bit in Z-register that is mapped to PCMSB.
28.9.1. SPMCR – Store Program Memory Control Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses.
Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Zpointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles.
29. 29.1. Memory Programming Program and Data Memory Lock Bits The ATmega32A provides six Lock bits. These can be left unprogrammed ('1') or can be programmed ('0') to obtain the additional features listed in table Lock Bit Protection Modes below. The Lock Bits can only be erased to “1” with the Chip Erase command. Table 29-1. Lock Bit Byte Bit No.
Memory Lock Bits Protection Type LB Mode LB2 LB1 4 0 1 BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 3 0 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
Fuse High Byte Bit No. Description Default Value BOOTSZ0 1 Select Boot Size (see table Boot Size Configuration in section ATmega32A Boot Loader Parameters for details) 0 (programmed)(3) BOOTRST 0 Select Reset Vector 1 (unprogrammed) Note: 1. The SPIEN Fuse is not accessible in SPI Serial Programming mode. 2. The CKOPT Fuse functionality depends on the setting of the CKSEL bits, see Clock Sources for details. 3. The default value of BOOTSZ1:0 results in maximum Boot Size.
29.2.1. Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 29.3. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
29.6.1. Signal Names In this section, some pins of this device are referenced by signal names describing their functionality during parallel programming, refer to the following figure and table Pin Name Mapping in this section. Pins not described in the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 29-9. When pulsing WR or OE, the command loaded determines the action executed.
Signal Name in Programming Mode Pin Name I/O Function BS2 PA0 I DATA PB7-0 I/O Bi-directional Data bus (Output when OE is low) Byte Select 2 (“0” selects Low byte, “1” selects second High byte) Table 29-8. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 29-9.
Table 29-12. Number of Words in a Page and number of Pages in the EEPROM EEPROM Size Page Size PCWORD Number of Pages PCPAGE EEAMSB 1Kbyte 4 bytes EEA[1:0] 256 EEA[9:2] 9 29.7. Parallel Programming 29.7.1. Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. 2. 3. 4. Apply 4.5 - 5.5V between VCC and GND, and wait at least 100µs.
5. 6. 29.7.4. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. Wait until RDY/BSY goes high before loading a new command. Programming the Flash The Flash is organized in pages, see Table 29-10. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: Step A. Load Command “Write Flash”. 1. Set XA1, XA0 to “10”.
4. Give XTAL1 a positive pulse. This loads the address high byte. Step H. Program Page. 1. Set BS1 = “0” 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 3. Wait until RDY/BSY goes high (Refer to the last figure on programming the Flash waveforms in this section). Step I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. Step J. End Page Programming. 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2.
Figure 29-3. Programming the Flash Waveforms F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: “XX” is don’t care. The letters refer to the programming description above. 29.7.5. Programming the EEPROM The EEPROM is organized in pages, see Table 29-12, in the Page Size section. When programming the EEPROM, the program data is latched into a page buffer.
Figure 29-4. Programming the EEPROM Waveforms K DATA A G B 0x11 ADDR. HIGH ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 29.7.6. Reading the Flash The algorithm for reading the Flash memory is as follows (Please refer to Programming the Flash in this chapter for details on Command and Address loading): 1. 2. 3. 4. 5. 6. 29.7.7.
1. 2. 3. 4. 5. Step A: Load Command “0100 0000”. Step C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. Set BS1 to “1” and BS2 to “0”. This selects high data byte. Give WR a negative pulse and wait for RDY/BSY to go high. Set BS1 to “0”. This selects low data byte. Figure 29-5. Programming the FUSES Waveforms Write Fuse Low byte A DATA 0x40 A C DATA Write Fuse high byte XX 0x40 C DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 29.7.10.
4. 5. Set OE to “0”, BS2 to “0”, and BS1 to “1”. The status of the Lock Bits can now be read at DATA (“0” means programmed). Set OE to “1”. Figure 29-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fus e low byte DATA 0 Lock bits 1 Fus e high byte 1 BS 1 BS 2 29.7.12. Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (Please refer to Programming the Flash for details on Command and Address loading): 1. 2. 3. 4.
Figure 29-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in the first figure in this section (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 29-9.
Symbol Parameter Min Typ Max Units tXLPH XTAL1 Low to PAGEL high 0 ns tPLXH PAGEL low to XTAL1 high 150 ns tBVPH BS1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2/1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns tWLWH WR Pulse Width Low 150 ns tWLRL WR Low to RDY/BSY Low 0 1 μs tWLRH WR Low to RDY/BSY High(1) 3.7 4.
Figure 29-10. Serial Programming and Verify(1) +2.7 - 5.5V VCC MOS I PB5 MIS O PB6 S CK PB7 +2.7 - 5.5V (2) AVCC XTAL1 RES ET GND Note: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3 < AVCC < VCC + 0.3, however, AVCC should always be within 2.7 - 5.5V.
2. 3. 4. 5. 6. 7. 8. 9. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted.
Table 29-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location, VCC = 5V ± 10% Symbol Minimum Wait Delay tWD_FUSE 4.5ms tWD_FLASH 4.5ms tWD_EEPROM 9ms tWD_ERASE 9ms Figure 29-11. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 29-16.
Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation Write Fuse Bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. See Table 29-4 for details. Write Fuse High Bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. See Table 29-3 for details. Read Fuse Bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse Bits. “0” = programmed, “1” = unprogrammed. See table Table 29-4 for details.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which data register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in the figure below. Figure 29-12.
Register is selected as Data Register. Note that the reset will be active as long as there is a logic 'one' in the Reset Chain. The output from this chain is not latched. The active states are: • Shift-DR: The Reset Register is shifted by the TCK input. 29.10.3. PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-bit Programming Enable Register is selected as data register.
29.10.7. Data Registers The data registers are selected by the JTAG instruction registers described in section Programming Specific JTAG Instructions. The data registers relevant for programming operations are: • • • • • Reset Register Programming Enable Register Programming Command Register Virtual Flash Page Load Register Virtual Flash Page Read Register 29.10.8. Reset Register The Reset Register is a Test Data Register used to reset the part during programming.
Programming Instruction Set is shown in the following table. The state machine sequence when shifting in the programming commands is illustrated in the last figure in this section. Figure 29-14. Programming Command Register TDI S T R O B E S Fla s h EEP ROM Fus e s Lock Bits A D D R E S S / D A T A TDO Table 29-17.
Instruction TDI sequence TDO sequence Notes 2g. Write Flash Page 0110111_00000000 0110101_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 2h. Poll for Page Write complete 0110111_00000000 xxxxxox_xxxxxxxx 3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 3d.
Instruction TDI sequence TDO sequence Notes 6c. Write Fuse High byte 0110111_00000000 0110101_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 6d. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 6e. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6f.
Instruction TDI sequence TDO sequence 10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 10c. Read Calibration Byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo Notes Note: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is normally the case). 2. Repeat until o = “1”. 3.
Figure 29-15. State Machine Sequence for Changing/Reading the Data Word 1 Te s t-Logic-Re s e t 0 0 Run-Te s t/Idle 1 S e le ct-DR S ca n 1 S e le ct-IR S ca n 0 0 1 1 Ca pture -DR Ca pture -IR 0 0 S hift-DR S hift-IR 0 1 Exit1-DR 1 Exit1-IR 0 0 Pa us e -DR 0 0 Pa us e -IR 1 1 0 Exit2-DR Exit2-IR 1 1 Upda te -DR 1 0 1 1 0 1 Upda te -IR 0 1 0 29.10.11.
Figure 29-16. Virtual Flash Page Load Register S TROBES TDI S ta te ma chine ADDRES S Fla s h EEP ROM Fus e s Lock Bits D A T A TDO 29.10.12. Virtual Flash Page Read Register The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte by byte.
Figure 29-17. Virtual Flash Page Read Register S TROBES TDI S ta te ma chine ADDRES S Fla s h EEP ROM Fus e s Lock Bits D A T A TDO 29.10.13. Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 29-17. 29.10.14. Entering Programming Mode 1. 2. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. 29.10.15. Leaving Programming Mode 1. 2. 3. 4.
1. 2. 3. 4. 5. 6. 7. 8. 9. Enter JTAG instruction PROG_COMMANDS. Enable Flash write using programming instruction 2a. Load address high byte using programming instruction 2b. Load address low byte using programming instruction 2c. Load data using programming instructions 2d, 2e and 2f. Repeat steps 4 and 5 for all instruction words in the page. Write the page using programming instruction 2g.
6. 7. Enter JTAG instruction PROG_COMMANDS. Repeat steps 3 to 6 until all data have been read. Related Links Parallel Programming Characteristics on page 339 29.10.19. Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed. See Performing Chip Erase. 1. 2. 3. 4. 5. 6. 7. 8. 9. Enter JTAG instruction PROG_COMMANDS. Enable EEPROM write using programming instruction 4a. Load address high byte using programming instruction 4b.
Related Links Parallel Programming Characteristics on page 339 29.10.22. Programming the Lock Bits 1. 2. 3. 4. 5. Enter JTAG instruction PROG_COMMANDS. Enable Lock bit write using programming instruction 7a. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. Write Lock bits using programming instruction 7c.
30. Electrical Characteristics Table 30-1. Absolute Maximum Ratings* 30.1. Operating Temperature -55°C to +125°C Storage Temperature -65°C to +150°C Voltage on any Pin except RESET with respect to Ground -0.5V to VCC +0.5V Voltage on RESET with respect to Ground -0.5V to +13.0V Maximum Operating Voltage 6.0V DC Current per I/O Pin 40.0mA DC Current VCC and GND Pins 200.0mA and 400.
Symbol Parameter Condition Min Typ Max Units Output Low Voltage(3) (Ports A,B,C,D) IOL = 20mA, VCC = 5V 0.7 V IOL = 10mA, VCC = 3V 0.5 V Output High Voltage(4) (Ports A,B,C,D) IOH = -20mA, VCC = 5V 4.2 V IOH = -10mA, VCC = 3V 2.2 V IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1 μA IIH Input Leakage Current I/O Pin VCC = 5.
3.3. The sum of all IOL, for ports B0 - B7, C0 - C7, D0 - D7 and XTAL2, should not exceed 100mA. TQFP and QFN/MLF Package: 4. 3.1. 3.2. 3.3. 3.4. 3.5. The sum of all IOL, for all ports, should not exceed 400 mA. The sum of all IOL, for ports A0 - A7, should not exceed 100 mA. The sum of all IOL, for ports B0 - B4, should not exceed 100 mA. The sum of all IOL, for ports B3 - B7, XTAL2, D0 - D2, should not exceed 100 mA. The sum of all IOL, for ports D3 - D7, should not exceed 100 mA. 3.6.
30.2. Speed Grades Figure 30-1. Maximum Frequency vs. Vcc 16 MHz 8 MHz S a fe Ope ra ting Are a 2.7V 30.3. Clock Characteristics 30.3.1. External Clock Drive Waveforms 4.5V 5.5V Figure 30-2. External Clock Drive Waveforms VIH1 VIL1 30.3.2. External Clock Drive Table 30-3. External Clock Drive Symbol Parameter VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Units Min Max Min Max 8 0 16 1/tCLCL Oscillator Frequency 0 tCLCL Clock Period 125 62.
Table 30-4. External RC Oscillator, Typical Frequencies R [kΩ](1) C [pF] f(2) 33 22 650kHz 10 22 2.0MHz Note: 1. R should be in the range 3kΩ - 100kΩ, and C should be at least 20pF. The C values given in the table includes pin capacitance. This will vary with package type. 2. The frequency will vary with package type and board layout. 30.4. System and Reset Characteristics Table 30-5.
Table 30-6. Two-wire Serial Bus Requirements Symbol Parameter Condition Min Max Units V VIL Input Low-voltage -0.5 0.3VCC VIH Input High-voltage 0.7VCC VCC + 0.5 V Vhys(1) Hysteresis of Schmitt Trigger Inputs 0.05VCC(2) – V VOL(1) Output Low-voltage 0 0.
Symbol Parameter Condition Min Max Units tBUF fSCL ≤ 100kHz 4.7 – μs fSCL > 100kHz 1.3 – μs Bus free time between a STOP and START condition Note: 1. In ATmega32A, this parameter is characterized and not 100% tested. 2. Required only for fSCL > 100kHz. 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all ATmega32A Two-wire Serial Interface operation.
Description Mode Min 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 16 SCK to SS high Slave 17 SS high to tri-state Slave 18 SS low to SCK Slave Typ Max 15 ns 20 10 2 • tck Figure 30-4. SPI interface timing requirements (Master Mode) SS 6 1 S CK (CP OL = 0) 2 2 S CK (CP OL = 1) 4 MIS O (Da ta Input) 5 3 MS B ... LS B 8 7 MOS I (Da ta Output) MS B ...
30.7. ADC Characteristics Table 30-8. ADC Characteristics Symbol Parameter Condition Min Typ Max Units Resolution Single Ended Conversion 10 Bits Absolute accuracy (Including INL, DNL, Quantization Error, Gain, and Offset Error) Single Ended Conversion 1.5 LSB 3 LSB 1.5 LSB 3 LSB 0.75 LSB 0.25 LSB 0.75 LSB 0.
Symbol Parameter Condition Min Typ Max Units Clock Frequency 50 1000 kHz AVCC Analog Analog Supply Voltage VCC 0.3(1) VCC + 0.3(2) V VREF Reference Voltage 2.0 AVCC V VIN Input voltage GND VREF V ADC conversion output 0 1023 LSB Input bandwidth 2.3 38.5 kHz 2.56 2.7 V VINT Internal Voltage Reference RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Typ Max Units Note: 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V. Table 30-9.
Symbol Parameter Condition Typ Max Units 0.75 LSB 0.75 LSB 2 LSB Gain = 1x 1.6 % Gain = 10x 1.5 % Gain = 200x 0.2 % Gain = 1x 1 LSB 1.5 LSB 4.
Symbol Parameter Condition Min Typ Max Units RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Note: 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V.
31. Typical Characteristics Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. The power consumption in Power-down mode is independent of clock selection.
Figure 31-2. Active Supply Current vs. Frequency (1 - 16MHz) ACTIVE S UP P LY CURRENT vs . FREQUENCY 1 -16 MHz ICC (mA) 18 16 5.5V 14 5.0V 12 4.5V 10 4.0V 8 3.6V 6 3.3V 4 2.7V 2 0 0 2 4 6 8 10 12 14 16 Fre que ncy (MHz) Figure 31-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 8 MHz 12 25 °C 10 85 °C -40 °C ICC (mA) 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
Figure 31-4. Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 4 MHz 6 25 °C 85 °C 5 -40 °C ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-5. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 1 MHz 1.6 25 °C 85 °C 1.4 -40 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.
Figure 31-6. Active Supply Current vs. VCC (External Oscillator, 32kHz) ACTIVE S UP P LY CURRENT vs . VCC EXTERNAL OS CILLATOR, 32 kHz 160 25 °C 140 120 ICC (uA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 31-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0MHz) IDLE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz 0.7 0.6 5.5 V 0.5 ICC (mA) 31.2. 5.0 V 0.4 4.5 V 4.0 V 3.6 V 3.3 V 0.3 0.2 2.7 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 31-8. Idle Supply Current vs. Frequency (1 MHz - 16 MHz) IDLE S UP P LY CURRENT vs . FREQUENCY 1 - 16 MHz 8 7 5.5V 6 5.0V ICC (mA) 5 4.5V 4 4.0V 3 3.6V 2 2.7V 1 3.3V 0 0 2 4 6 8 10 12 14 16 Fre que ncy (MHz) Figure 31-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 8 MHz 5 -40 °C 25 °C 85 °C ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
Figure 31-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 4 MHz 2.5 -40 °C 25 °C 85 °C ICC (mA) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 1 MHz 0.8 0.7 85 °C 0.6 25 °C -40 °C ICC (mA) 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.
Figure 31-12. Idle Supply Current vs. VCC (External Oscillator, 32kHz) IDLE S UP P LY CURRENT vs . VCC EXTERNAL OS CILLATOR, 32 kHz 40 35 25 °C 30 ICC (uA) 25 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 31-13. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) P OWER-DOWN S UP P LY CURRENT vs . VCC WATCHDOG TIMER DIS ABLED 2 85 °C 1.6 -40 °C 1.2 ICC (uA) 31.3. 25 °C 0.8 0.4 0 2.5 3 3.5 4 4.5 5 5.
Figure 31-14. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) P OWER-DOWN S UP P LY CURRENT vs . VCC WATCHDOG TIMER ENABLED 20 85 °C -40 °C 25 °C 16 ICC (uA) 12 8 4 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply current Figure 31-15. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) P OWER-S AVE S UP P LY CURRENT vs . VCC WATCHDOG TIMER DIS ABLED 20 25 °C 16 12 ICC (uA) 31.4. 8 4 0 2.5 3 3.5 4 4.5 5 5.
31.5. Standby Supply Current Figure 31-16. Standby Supply Current vs. VCC (WDT Disabled) S TANDBY S UP P LY CURRENT vs . VCC WATCHDOG TIMER DIS ABLED 0.16 6MHz_xta l 6MHz_re s 0.14 0.12 4MHz_re s 4MHz_xta l ICC (mA) 0.1 0.08 2MHz_re s 2MHz_xta l 450kHz_re s 1MHz_re s 0.06 0.04 0.02 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-up Figure 31-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O P IN P ULL-UP RES IS TOR CURRENT vs .
Figure 31-18. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE VCC = 2.7V 70 25 °C -40 °C 60 85 °C IOP (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 31-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RES ET P ULL-UP RES IS TOR CURRENT vs .
Figure 31-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE VCC = 2.7V 60 50 IRES ET (uA) 40 30 20 10 -40 °C 0 25 °C 85 °C 0 0.5 1 1.5 2 2.5 3 VRES ET(V) Pin Driver Strength Figure 31-21. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O P IN S OURCE CURRENT vs . OUTP UT VOLTAGE VCC = 5V 80 70 25 °C 60 -40 °C 85 °C 50 IOH (mA) 31.7. 40 30 20 10 0 3 3.4 3.8 4.2 4.
Figure 31-22. I/O Pin Source Current vs. Output Voltage (VCC = 3V) I/O P IN S OURCE CURRENT vs . OUTP UT VOLTAGE VCC = 3V 35 -40 °C 25 °C 30 85 °C IOH (mA) 25 20 15 10 5 0 1 1.5 2 2.5 3 VOH (V) Figure 31-23. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O P IN S INK CURRENT vs . OUTP UT VOLTAGE VCC = 5V 90 -40 °C 80 25 °C 70 85 °C IOL (mA) 60 50 40 30 20 10 0 0 0.5 1 1.
Figure 31-24. I/O Pin Sink Current vs. Output Voltage (VCC = 3V) I/O P IN S INK CURRENT vs . OUTP UT VOLTAGE VCC = 3V IOL (mA) 45 40 -40 °C 35 25 °C 30 85 °C 25 20 15 10 5 0 0 0.5 1 1.5 2 VOL (V) Pin Thresholds and Hysteresis Figure 31-25. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC VIH, IO P IN READ AS '1' 3 85 °C 25 °C 2.5 -40 °C 2 Thre s hold (V) 31.8. 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 31-26. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC VIL, IO P IN READ AS '0' 2.5 85 °C 25 °C -40 °C Thre s hold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-27. I/O Pin Input Hysteresis vs. VCC I/O P IN INP UT HYS TERES IS vs . VCC 0.6 -40 °C 25 °C Input Hys te re s is (mV) 85 °C 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.
Figure 31-28. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) RES ET INP UT THRES HOLD VOLTAGE vs . VCC VIH, IO P IN READ AS '1' 2.5 Thre s hold (V) 2 -40 °C 1.5 25 °C 85 °C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-29. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) RES ET INP UT THRES HOLD VOLTAGE vs . VCC VIL, IO P IN READ AS '0' 2.5 85 °C 25 °C -40 °C Thre s hold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 31-30. Reset Input Pin Hysteresis vs. VCC RES ET P IN INP UT HYS TERES IS vs . VCC 0.5 Input Hys te re s is (mV) 0.4 0.3 -40 °C 0.2 25 °C 0.1 85 °C 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) BOD Thresholds and Analog Comparator Offset Figure 31-31. BOD Thresholds vs. Temperature (BOD Level is 4.0V) BOD THRES HOLDS vs . TEMP ERATURE BOD LEVEL IS 4.0 V 4.1 Ris ing VCC 4 Thre s hold (V) 31.9. 3.9 Fa lling VCC 3.
Figure 31-32. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRES HOLDS vs . TEMP ERATURE BOD LEVEL IS 2.7 V 2.9 Ris ing VCC Thre s hold (V) 2.8 2.7 Fa lling VCC 2.6 -60 -40 -20 0 20 40 60 80 100 Te mpe ra ture (C) Figure 31-33. Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs . VCC 1.25 1.248 Ba ndga p Volta ge (V) 1.246 1.244 1.242 1.24 25 °C 1.238 85 °C 1.236 -40 °C 1.234 1.232 2.5 ¨ 3 3.5 4 4.5 5 5.
31.10. Internal Oscillator Speed Figure 31-34. Watchdog Oscillator Frequency vs. VCC WATCHDOG OS CILLATOR FREQUENCY vs . VCC 1320 -40 °C 25 °C 1300 1280 85 °C F RC (kHz) 1260 1240 1220 1200 1180 1160 1140 1120 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-35. Calibrated 8MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 8.5 8.3 8.1 F RC (MHz) 7.9 5.5 5.0 4.5 4.0 7.7 7.5 7.3 V V V V 3.6 V 3.3 V 7.1 6.9 2.7 V 6.7 6.
Figure 31-36. Calibrated 8MHz RC Oscillator Frequency vs. VCC CALIBRATED 8 MHz RC OS CILLATOR FREQUENCY vs . VCC 9 8.5 -40 °C 25 °C F RC (MHz) 8 85 °C 7.5 7 6.5 6 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-37. Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8 MHz RC OS CILLATOR FREQUENCY vs .
Figure 31-38. Calibrated 4MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 4.2 4.1 F RC (MHz) 4 5.5 5.0 4.5 4.0 3.9 3.8 V V V V 3.6 V 3.3 V 3.7 2.7 V 3.6 3.5 -60 -40 -20 0 20 40 60 80 100 Te mpe ra ture Figure 31-39. Calibrated 4MHz RC Oscillator Frequency vs. VCC CALIBRATED 4 MHz RC OS CILLATOR FREQUENCY vs . VCC 4.2 -40 °C 4.1 25 °C F RC (MHz) 4 85 °C 3.9 3.8 3.7 3.6 3.5 2.5 3 3.5 4 4.5 5 5.
Figure 31-40. Calibrated 4MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4 MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 8 7 -40 °C 25 °C 6 85 °C F RC (MHz) 5 4 3 2 1 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OS CCAL (X1) Figure 31-41. Calibrated 2MHz RC Oscillator Frequency vs. Temperature CALIBRATED 2 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 2.1 2.05 F RC (MHz) 2 5.5 5.0 4.5 4.0 3.6 3.3 1.95 1.9 V V V V V V 1.85 2.7 V 1.
Figure 31-42. Calibrated 2MHz RC Oscillator Frequency vs. VCC CALIBRATED 2 MHz RC OS CILLATOR FREQUENCY vs . VCC 2.1 -40 °C 25 °C 2 F RC (MHz) 85 °C 1.9 1.8 1.7 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-43. Calibrated 2MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 2 MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 4 -40 °C 3.5 25 °C 85 °C 3 F RC (MHz) 2.5 2 1.5 1 0.
Figure 31-44. Calibrated 1MHz RC Oscillator Frequency vs. Temperature CALIBRATED 1 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 1.04 1.02 F RC (MHz) 1 5.5 5.0 4.5 4.0 3.6 3.3 0.98 0.96 V V V V V V 0.94 2.7 V 0.92 -60 -40 -20 0 20 40 60 80 100 Te mpe ra ture Figure 31-45. Calibrated 1MHz RC Oscillator Frequency vs. VCC CALIBRATED 1 MHz RC OS CILLATOR FREQUENCY vs . VCC 1.04 1.02 -40 °C 25 °C F RC (MHz) 1 85 °C 0.98 0.96 0.94 0.92 2.5 3 3.5 4 4.5 5 5.
Figure 31-46. Calibrated 1MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 1 MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 2 -40 °C 25 °C 85 °C 1,8 1,6 F RC (MHz) 1,4 1,2 1 0,8 0,6 0,4 0,2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OS CCAL (X1) 31.11. Current Consumption of Peripheral Units Figure 31-47. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs . VCC 20 -40 °C 25 °C 18 16 85 °C 14 ICC (uA) 12 10 8 6 4 2 0 2.5 3 3.5 4 4.
Figure 31-48. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs . V CC AREF = AVCC 350 85 °C 25 °C 300 -40 °C ICC (uA) 250 200 150 100 50 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-49. AREF External Reference Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs . VCC 200 85 °C 25 °C -40 °C ICC (uA) 150 100 50 0 2.5 3 3.5 4 4.5 5 5.
Figure 31-50. Analog Comparator Current vs. VCC ANALOG COMP ARATOR CURRENT vs . VCC 100 90 80 85 °C ICC (uA) 70 25 °C -40 °C 60 50 40 30 20 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-51. Programming Current vs. VCC P ROGRAMMING CURRENT vs . VCC 9 8 -40 °C 7 25 °C ICC (mA) 6 85 °C 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
31.12. Current Consumption in Reset and Reset Pulsewidth Figure 31-52. Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) RES ET S UP P LY CURRENT vs . VCC EXCLUDING CURRENT THROUGH THE RES ET P ULLUP 3 2.5 5.5 V 5.0 V ICC (mA) 2 4.5 V 1.5 4.0 V 3.6 V 3.3 V 1 2.7 V 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Figure 31-53. Reset Supply Current vs.
Figure 31-54. Minimum Reset Pulse Width vs. VCC MINIMUM RES ET P ULS E WIDTH vs . VCC 800 700 P uls e width (ns ) 600 500 400 85 °C 25 °C -40 °C 300 200 100 0 2.5 3 3.5 4 4.5 5 5.
32.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x15 (0x35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 0x14 (0x34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0x13 (0x33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 0x10 (0x
33.
BRANCH INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks Indirect Call to (Z) PC ← Z None 3 Direct Subroutine Call PC ← k None 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 ICALL CALL(1) k CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd - Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd - K Z, N,V,C,
BIT AND BIT-TEST INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C¬Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0:6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3:0)←Rd(7:4),Rd(7:4)¬Rd(3
DATA TRANSFER INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec.
MCU CONTROL INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Note: 1. Instruction not available in all devices.
34. Packaging Information 34.1. 44-pin TQFP P IN 1 IDENTIFIER P IN 1 B e E1 E A1 A2 D1 D C 0°~7° L A COMMON DIMENS IONS (Unit of Me a s ure = mm) MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 S YMBOL Note s : 1. This pa cka ge conforms to J EDEC re fe re nce MS -026, Va ria tion ACB. 2. Dime ns ions D1 a nd E1 do not include mold protrus ion. Allowa ble protrus ion is 0.25mm pe r s ide . Dime ns ions D1 a nd E1 a re ma ximum pla s tic body s ize dime ns ions including mold mis ma tch. 3.
34.2. 40-pin PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). SYMBOL MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.
34.3. 44-pin VQFN D Marked Pin# 1 I D E SE ATING PLANE A1 TOP VIEW A3 A K L Pin #1 Co rne r D2 1 2 3 Option A SIDE VIEW Pin #1 Triangl e COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 SYMBOL E2 Option B K Option C b e Pin #1 Cham fe r (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW A3 0.20 REF b 0.18 0.23 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note : JEDEC Standard MO-220, Fig .
35. Errata 35.1. ATmega32A, rev. J to rev. K • • • • First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR. 35.2. ATmega32A, rev. G to rev. I • • • • First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. 1.
– 4. If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega32A must be the fist device in the chain. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR.
36. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section refers to the document revision. 36.1. 8155I - 08/2016 1. 36.2. 8155H - 08/2016 1. 2. 3. 36.3. Updated the Features with Capacitive touch sensing capability. Added Errata: ATmega32A, rev. J to rev. K. 8155D – 10/2013 1. 36.7. New workflow used for the publication. 8155E - 02/2014 1. 2. 36.6. Updated the pinout.
36.8. 8155B – 07/2009 1. 2. 36.9. Updated Errata. Updated the last page with Atmel’s new addresses. 8155A – 06/2008 1. Initial revision (Based on the ATmega32/L datasheet 2503N-AVR-06/08) Changes done compared ATmega32/L datasheet 2503N-AVR-06/08: – – – – – – Updated description in Stack Pointer. All Electrical characteristics is moved to Electrical Characteristics. Register descriptions are moved to sub sections at the end of each chapter.
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