Datasheet

4. Block Diagram
Figure 4-1. Block Diagram
CPU
USART 0
SPI 1
ADC
ADC[7:0]
AREF
RxD0
TxD0
XCK0
MISO1
MOSI1
SCK1
SS1
I/O
PORTS
D
A
T
A
B
U
S
GPIOR[2:0]
SRAM
OCD
EXTINT
FLASH
NVM
programming
debugWire
I
N
/
O
U
T
D
A
T
A
B
U
S
TC 0
(8-bit)
SPI 0
AC
AIN0
AIN1
ACO
EEPROM
EEPROMIF
PTC
X[15:0]
Y[23:0]
TC 1
(16-bit)
OC1A/B
T1
ICP1
TC 3
(16-bit)
TC 4
(16-bit)
OC3A/B
T3
ICP3
OC4A/B
T4
ICP4
TC 2
(8-bit async)
TWI 0
TWI 1
SDA0
SCL0
SDA1
SCL1
USART 1
RxD1
TxD1
XCK1
Internal
Reference
Watchdog
Timer
Power
management
and clock
control
VCC
GND
Clock generation
8MHz
Calib RC
128kHz int
osc
32.768kHz
XOSC
External
clock
Power
Supervision
POR/BOD &
RESET
XTAL2 /
TOSC2
RESET
XTAL1 /
TOSC1
16MHz LP
XOSC
Crystal failure detection
PCINT[27:0]
INT[1:0]
T0
OC0A
OC0B
MISO0
MOSI0
SCK0
SS0
OC2A
OC2B
PB[7:0]
PC[6 :0]
PD[7:0]
PE[3:0]
PE[3:2], PC[5:0]
AREF
PB[5:0], PE[1:0], PD[7:0]
PB[5:0], PE[1:0], PD[7:0], PE[3:2], PC[5:0]
PE[3:0], PD[7:0], PC[6:0], PB[7:0]
PD3, PD2
PB1, PB2
PD5
PB0
PB3
PD3
PD0, PD2
PE3
PE2
PD1, PD2
PE1
PE0
PD0
PD1
PD4
PC0
PE3
PC1
PE2
PC4
PC5
PE0
PE1
PB4
PB3
PB5
PD4
PD6
PD5
PB4
PB3
PB5
PB2
SPIPROG
PARPROG
PD6
PD7
PE0
ATmega328PB
© 2017 Microchip Technology Inc.
Datasheet Summary
40001907A-page 7