Datasheet

signal is left floating or have an analog signal level close to V
CC
/2, the input buffer will use excessive
power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close
to V
CC
/2 on an input pin can cause significant current even in active mode. Digital input buffers can be
disabled by writing to the Digital Input Disable Registers (DIDR0 for ADC, DIDR1 for AC).
Related Links
Digital Input Enable and Sleep Modes
13.11.7 On-chip Debug System
If the on-chip debug system is enabled by the DWEN fuse and the chip enters Sleep mode, the main
clock source is enabled and hence always consumes power. In the deeper Sleep modes, this will
contribute significantly to the total current consumption.
13.12 Register Description
ATmega328PB
Power Management and Sleep Modes
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 68