Datasheet

Figure 12-1. System Clock Generation with CFD Mechanism

Clock Failure Detection

circuit

Low Power Crystal Oscillator

128kHz Internal Oscillator

Calibrated Internal RC Oscillator

External Clock

System

clock

XOSC CKSEL

Calibrated RC Oscillator

(CKSEL: 4'b 0010

CLKPS: 4'b 0011)

XOSC Failed

CKSEL

WDT 128kHz CLK

XOSC

(External CLK/

Low Power Crystal Osc CLK)

Clock Failure Detection

To start the CFD operation, the user must write a one to the CFD fuse bit in the Extended Fuse Byte

(EFB.CFD). After the start or restart of the XOSC, the CFD does not detect failure until the start-up time is

elapsed. Once the XOSC Start-Up Time is elapsed, the XOSC clock is constantly monitored.

If the external clock is not provided, the device will automatically switch to calibrated RC oscillator output.

When the failure is detected, the failure status is asserted, i.e Failure Detection Interrupt Flag bit in the

XOSC Failure Detection Control And Status Register (XFDCSR.XFDIF) is set. The Failure Detection

interrupt flag is generated, when the Interrupt Enable bit in the XOSC Failure Detection Control And

Status Register (XFDCSR.XFDIE) is set. The XFDCSR.XFDIF reflects the current XOSC clock activity.

The detection will be automatically disabled when chip goes to power save/down sleep mode and

enabled by itself when chip enters back to active mode.

Clock Switch

When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an

active clock. The safe clock source is the calibrated RC oscillator clock (CKSEL: 4’b0010). The clock

source can be downscaled with a configurable prescaler to ensure that the clock frequency does not

exceed the operating conditions selected by the application after switching. To use the original clock

source, the user must provide a reset. When using CFD and clock failure has occurred the system

operates using 1 MHz internal fallback clock. The system will try to resume to original clock source either

via Power-On-Reset (POR) or via external RESET.

ATmega328PB

CFD - Clock Failure Detection mechanism

Datasheet Complete

DS40001906C-page 60