Datasheet

12. CFD - Clock Failure Detection mechanism

12.1 Overview

The Clock Failure Detection mechanism for the device is enabled by CFD fuse in the Extended Fuse

Byte. CFD operates with a 128 kHz internal oscillator which will be enabled automatically when CFD is

enabled.

12.2 Features

• Detection of the failure of the low power crystal oscillator and external clocks

• Operate with 128 kHz internal oscillator

• Switch the system clock to 1 MHz internal RC oscillator clock when clock failure happens

• Failure Detection Interrupt Flag (XFDIF) available for the status of CFD

12.3 Operations

The Clock Failure Detector (CFD) allows the user to monitor the low power crystal oscillator or external

clock signal. CFD monitors XOSC clock and if it fails it will automatically switch to a safe clock. When

operating on the safe clock the device will switch back to XOSC clock after Power-On or External Reset,

and continue monitoring XOSC clock for failures. The safe 1 MHz system clock is derived from the 8 MHz

internal RC system clock. After switching to safe 1 MHz clock the user can write the System Clock

Prescale Register (CLKPR) to increase the frequency. This allows configuring the safe clock in order to

fulfill the operative conditions of the microcontroller.

Because the XOSC failure is monitored by the CFD circuit operating with the internal 128 kHz oscillator,

the current consumption of the 128 kHz oscillator will be added into the total power consumption of the

chip when CFD is enabled. CFD should be enabled only if the system clock (XOSC) frequency is above

256 kHz.

ATmega328PB

CFD - Clock Failure Detection mechanism

Datasheet Complete

DS40001906C-page 59