Datasheet

11.9 Timer/Counter Oscillator
The device uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator.
See Low Frequency Crystal Oscillator for details on the oscillator and crystal requirements.
On this device, the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with EXTCLK. When
using the Timer/Counter Oscillator, the system clock needs to be four times the oscillator frequency. Due
to this and the pin sharing, the Timer/Counter Oscillator can only be used when the Calibrated Internal
RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if the Enable External Clock Input bit in the
Asynchronous Status Register (ASSR.EXCLK) is written to '1'. See the description of the Asynchronous
Operation of Timer/Counter2 for further description on selecting external clock as input instead of a
32.768 kHz watch crystal.
Related Links
8-bit Timer/Counter2 with PWM and Asynchronous Operation
11.10 System Clock Prescaler
The device has a system clock prescaler and the system clock can be divided by configuring the Clock
Prescale Register (CLKPR). This feature can be used to decrease the system clock frequency and the
power consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk
I/O
,
clk
ADC
, clk
CPU
, and clk
FLASH
are divided by a factor as shown in the CLKPR description.
When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in
the clock system. It also ensures that no intermediate frequency is higher than neither the clock
frequency corresponding to the previous setting nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may
be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler
- even if it were readable, the exact time it takes to switch from one clock division to the other cannot be
exactly predicted. From the time the Clock Prescaler Selection bits (CLKPS[3:0]) values are written, it
takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, two
active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period
corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change
the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to '1' and all other bits in CLKPR to zero:
CLKPR=0x80.
2. Within four cycles, write the desired value to CLKPS[3:0] while writing a zero to CLKPCE:
CLKPR=0x0N.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not
interrupted.
11.11 Register Description
ATmega328PB
System Clock and Clock Options
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 55