Datasheet

Figure 33-3. SPI Interface Timing Requirements (Master Mode)
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
6 1
2 2
34 5
8
7
Figure 33-4. SPI Interface Timing Requirements (Slave Mode)
MISO
(Data Output)
SCK
(CPOL = 1)
MOSI
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
10
11 11
1213 14
17
15
9
X
16
33.8 Two-Wire Serial Interface Characteristics
Table in this section describes the requirements for devices connected to the two-wire Serial Bus. The
two-wire Serial Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 33-5.
Table 33-9. Two-Wire Serial Bus Requirements
Symbol Parameter Condition Min. Max Units
V
IL
Input Low-voltage -0.5 0.3 V
CC
V
V
IH
Input High-voltage 0.7 V
CC
V
CC
+ 0.5 V
V
hys
(1)
Hysteresis of Schmitt Trigger
Inputs
0.05 V
CC
(2)
– V
ATmega328PB
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 412