Datasheet

10.3 SRAM Data Memory

The following figure shows how the device SRAM memory is organized.

The device is a complex microcontroller with more peripheral units than can be supported within the 64

locations reserved in the Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 -

0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower 2303 data memory locations address both the register file, the I/O memory, extended I/O

memory, and the internal data SRAM. The first 32 locations address the register file, the next 64 location

the standard I/O memory, then 160 locations of extended I/O memory, and the next 2K locations address

the internal data SRAM.

The five different addressing modes for the data memory cover:

• Direct

– The direct addressing reaches the entire data space.

• Indirect with Displacement

– The indirect with displacement mode reaches 63 address locations from the base address

given by the Y- or Z-register.

• Indirect

– In the register file, registers R26 to R31 feature the indirect addressing pointer registers.

• Indirect with Pre-decrement

– The address registers X, Y, and Z are decremented.

• Indirect with Post-increment

– The address registers X, Y, and Z are incremented.

The 32 general purpose working registers, 64 I/O registers, 160 extended I/O registers, and the 2 K bytes

of internal data SRAM in the device are all accessible through all these addressing modes.

Figure 10-2. Data Memory Map with 2048 Byte Internal Data SRAM

Load/Store

IN/OUT

0x0000 – 0x001F

0x0100

0x08FF

160 Ext I/O registers

64 I/O registers

32 registers

Internal SRAM

(2048x8)

0x0020 – 0x005F

0x0060 – 0x00FF

0x0000 – 0x001F

10.3.1 Data Memory Access Times

The internal data SRAM access is performed in two clk

CPU

cycles as described in the following Figure.

ATmega328PB

AVR Memories

Datasheet Complete

DS40001906C-page 34