Datasheet

26.9.6 TWI (Slave) Address Mask Register n
Name: TWAMR
Offset: 0xBD + n*0x20 [n=0..1]
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
TWAM[6:0]
Access
R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0
Bits 7:1 – TWAM[6:0] TWI (Slave) Address
The TWAMRn can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMRn can mask
(disable) the corresponding address bits in the TWI Address Register n (TWARn). If the mask bit is set to
one then the address match logic ignores the compare between the incoming address bit and the
corresponding bit in TWARn.
Figure 26-22. Address Match Logic, Example For TWI0
TWAR0
TWAMR0
Address
Bit 0
Address
Match
Address Bit Comparator 6:1
Address Bit Comparator 0
ATmega328PB
TWI - Two-Wire Serial Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 334