Datasheet

Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate

a STOP condition, but the TWI n returns to a well-defined unaddressed Slave mode and releases the

SCL and SDA lines to a high impedance state.

Bit 3 – TWWC TWI Write Collision Flag

The TWWC bit is set when attempting to write to the TWI n Data Register (TWDRn) when

TWCRn.TWINT is low. This flag is cleared by writing the TWDRn register when TWINT is high.

Bit 2 – TWEN TWI Enable

The TWEN bit enables TWI n operation and activates the TWI n interface. When TWEN is written to one,

the TWI n takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate

limiters and spike filters. If this bit is written to zero, the TWI n is switched OFF and all transmissions of

TWI n are terminated, regardless of any ongoing operation.

Bit 0 – TWIE TWI Interrupt Enable

When this bit is written to one, and the I-bit in the Status Register (SREG.I) is set, the TWI n interrupt

request will be activated for as long as the TWCRn.TWINT Flag is high.

ATmega328PB

TWI - Two-Wire Serial Interface

Datasheet Complete

DS40001906C-page 333