Datasheet

26.9.5 TWI Control Register n
Name: TWCR
Offset: 0xBC + n*0x20 [n=0..1]
Reset: 0x00
Property: -
The TWCRn is used to control the operation of the TWI n. It is used to enable the TWI n, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to
generate a stop condition, and to control halting of the bus while the data to be written to the bus are
written to the TWDRn. It also indicates a write collision if data is attempted written to TWDRn while the
register is inaccessible.
Bit 7 6 5 4 3 2 1 0
TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE
Access
R/W R/W R/W R/W R R/W R/W
Reset 0 0 0 0 0 0 0
Bit 7 – TWINT TWI Interrupt Flag
This bit is set by hardware when the TWI n has finished its current job and expects application software
response. If the I-bit in the Status Register (SREG.I) and the TWI Interrupt Enable bit in the TWI Control
Register n (TWCRn.TWIE) are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag
is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic
one to it.
Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also
note that clearing this flag starts the operation of the TWI n, so all accesses to the TWI Address Register
(TWARn), TWI Status Register (TWSRn), and TWI Data Register (TWDRn) must be complete before
clearing this flag.
Bit 6 – TWEA TWI Enable Acknowledge
This bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK
pulse is generated on the TWI n bus if the following conditions are met:
1. The device’s own slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWARn is set.
3. A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the two-wire Serial Bus
temporarily. Address recognition can then be resumed by writing the TWEA bit to one again.
Bit 5 – TWSTA TWI START Condition
The application writes the TWSTA bit to one when it desires TWI n to become a Master on the two-wire
Serial Bus. The TWI n hardware checks if the bus is available, and generates a START condition on the
bus if it is free. However, if the bus is not free, the TWI n waits until a STOP condition is detected, and
then generates a new START condition to claim the bus Master status. TWSTA must be cleared by
software when the START condition has been transmitted.
Bit 4 – TWSTO TWI STOP Condition
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the two-wire Serial Bus
TWI n. When the STOP condition is executed on the bus, the TWSTO bit is automatically cleared. In
ATmega328PB
TWI - Two-Wire Serial Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 332