Datasheet

26.9.4 TWI Data Register n

Name: TWDR

Offset: 0xBB + n*0x20 [n=0..1]

Reset: 0x01

Property: -

In Transmit mode, TWDRn contains the next byte to be transmitted. In Receive mode, the TWDRn

contains the last byte received. It is writable while the TWI n is not in the process of shifting a byte. This

occurs when the TWI Interrupt Flag in the TWI Control Register n (TWCRn.TWINT) is set by hardware.

Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in

TWDRn remains stable as long as TWCRn.TWINT is set. While data is shifted out, data on the bus is

simultaneously shifted in. TWDRn always contains the last byte present on the bus, except after a wake

up from a sleep mode by the TWI n interrupt. In this case, the contents of TWDRn is undefined. In the

case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK

bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.

Bit 7 6 5 4 3 2 1 0

TWD[7:0]

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 1

Bits 7:0 – TWD[7:0] TWI Data

These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the

two-wire Serial Bus.

ATmega328PB

TWI - Two-Wire Serial Interface

Datasheet Complete

DS40001906C-page 331