Datasheet

Table 24-14. USART Clock Polarity Settings
UCPOL Transmitted Data Changed (Output of TxDn
Pin)
Received Data Sampled (Input on RxDn
Pin)
0 Rising XCKn Edge Falling XCKn Edge
1 Falling XCKn Edge Rising XCKn Edge
Master SPI Mode: The UCPOL bit sets the polarity of the XCKn clock. The combination of the UCPOL
and UCPHA bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and
Timing for details.
ATmega328PB
USART - Universal Synchronous Asynchronous R...
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Datasheet Complete
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