Datasheet

Bit 3 – USBSn USART Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter n. The Receiver ignores this

setting.

Table 24-12. Stop Bit Settings

USBS Stop Bit(s)

0 1-bit

1 2-bit

This bit is reserved in Master SPI Mode (MSPIM).

Bit 2 – UCSZn1 / UDORDn USART Character Size / Data Order

UCSZ1[1:0]: USART Modes: The UCSZ1[1:0] bits combined with the UCSZ12 bit in UCSR1B sets the

number of data bits (Character Size) in a frame the Receiver and Transmitter use.

Table 24-13. Character Size Settings

UCSZ1[2:0] Character Size

000 5-bit

001 6-bit

010 7-bit

011 8-bit

100 Reserved

101 Reserved

110 Reserved

111 9-bit

UDORD0: Master SPI Mode: When set to one the LSB of the data word is transmitted first. When set to

zero the MSB of the data word is transmitted first. Refer to the USART in SPI Mode - Frame Formats for

details.

Bit 1 – UCSZn0 / UCPHAn USART Character Size / Clock Phase

UCSZ0: USART Modes: Refer to UCSZ1.

UCPHA: Master SPI Mode: The UCPHA bit setting determine if data is sampled on the leading edge

(first) or tailing (last) edge of XCK. Refer to the SPI Data Modes and Timing for details.

Bit 0 – UCPOLn Clock Polarity

USART n Modes: This bit is used for synchronous mode only. Write this bit to zero when asynchronous

mode is used. The UCPOL bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCKn).

ATmega328PB

USART - Universal Synchronous Asynchronous R...

Datasheet Complete

DS40001906C-page 288