Datasheet

24.12.4 USART Control and Status Register n C
Name: UCSRC
Offset: 0xC2 + n*0x08 [n=0..1]
Reset: 0x06
Property: -
Bit 7 6 5 4 3 2 1 0
UMSELn[1:0] UPMn[1:0] USBSn UCSZn1 /
UDORDn
UCSZn0 /
UCPHAn
UCPOLn
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 1 1 0
Bits 7:6 – UMSELn[1:0] USART Mode Select
These bits select the mode of operation of the USARTn
Table 24-10. USART Mode Selection
UMSEL[1:0] Mode
00 Asynchronous USART
01 Synchronous USART
10 Reserved
11 Master SPI (MSPIM)
(1)
Note:
1. The UDORD, UCPHA, and UCPOL can be set in the same write operation where the MSPIM is
enabled.
Bits 5:4 – UPMn[1:0] USART Parity Mode
These bits enable and set the type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The Receiver
will generate a parity value for the incoming data and compare it to the UPM setting. If a mismatch is
detected, the UPE Flag in UCSRnA will be set.
Table 24-11. USART Mode Selection
UPM[1:0] ParityMode
00 Disabled
01 Reserved
10 Enabled, Even Parity
11 Enabled, Odd Parity
These bits are reserved in Master SPI Mode (MSPIM).
ATmega328PB
USART - Universal Synchronous Asynchronous R...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 287