Datasheet

24.12.3 USART Control and Status Register n B
Name: UCSRB
Offset: 0xC1 + n*0x08 [n=0..1]
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n
Access
R/W R/W R/W R/W R/W R/W R R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 – RXCIEn RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the UCSRnA.RXC Flag. A USART Receive Complete interrupt
will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is written to
one and the RXC bit in UCSRnA is set.
Bit 6 – TXCIEn TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete interrupt will be
generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and
the TXC bit in UCSRnA is set.
Bit 5 – UDRIEn USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty interrupt will be
generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and
the UDRE bit in UCSRnA is set.
Bit 4 – RXENn Receiver Enable
Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for
the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FE, DOR,
and UPE Flags.
Bit 3 – TXENn Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation
for the TxDn pin when enabled. The disabling of the Transmitter (writing TXEN to zero) will not become
effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register
and Transmit Buffer Register does not contain data to be transmitted. When disabled, the Transmitter will
no longer override the TxDn port.
Bit 2 – UCSZn2 Character Size
The UCSZ2 bits combined with the UCSZ[1:0] bit in UCSRnC sets the number of data bits (Character
Size) in a frame the Receiver and Transmitter use.
This bit is reserved in Master SPI Mode (MSPIM).
Bit 1 – RXB8n Receive Data Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits.
Must be read before reading the low bits from UDRn.
This bit is reserved in Master SPI Mode (MSPIM).
ATmega328PB
USART - Universal Synchronous Asynchronous R...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 285