Datasheet

24.12.2 USART Control and Status Register n A
Name: UCSRA
Offset: 0xC0 + n*0x08 [n=0..1]
Reset: 0x20
Property: -
Bit 7 6 5 4 3 2 1 0
RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn
Access
R R/W R R R R R/W R/W
Reset 0 0 1 0 0 0 0 0
Bit 7 – RXCn USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is
empty (i.e., does not contain any unread data). If the receiver is disabled, the receive buffer will be
flushed and consequently, the RXC bit will become zero. The RXC flag can be used to generate a receive
complete interrupt (see the description of the RXCIE bit).
Bit 6 – TXCn USART Transmit Complete
This flag bit is set when the entire frame in the transmit shift register has been shifted out and there are
no new data currently present in the transmit buffer (UDRn). The TXC flag bit is automatically cleared
when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
The TXC flag can generate a transmit complete interrupt (see the description of the TXCIE bit).
Bit 5 – UDREn USART Data Register Empty
The UDRE flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDRE is one, the
buffer is empty, and therefore ready to be written. The UDRE flag can generate a data register empty
interrupt (see the description of the UDRIE bit). UDRE is set after a reset to indicate that the transmitter is
ready.
Bit 4 – FEn Frame Error
This bit is set if the next character in the receive buffer had a frame error when received. I.e., when the
first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer
(UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero
when writing to UCSRnA.
This bit is reserved in Master SPI Mode (MSPIM).
Bit 3 – DORn Data OverRun
This bit is set if a data overrun condition is detected. A data overrun occurs when the receive buffer is full
(two characters), it is a new character waiting in the receive shift register, and a new start bit is detected.
This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to
UCSRnA.
This bit is reserved in MSPIM.
Bit 2 – UPEn USART Parity Error
This bit is set if the next character in the receive buffer had a parity error when received and the parity
checking was enabled at that point (UCSRnC.UPM1 = 1). This bit is valid until the receive buffer (UDRn)
is read. Always set this bit to zero when writing to UCSRnA.
ATmega328PB
USART - Universal Synchronous Asynchronous R...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 283