Datasheet
• Idle sleep mode: system clock frequency divided by four
• Standby or Power-down: 500 kbps
The maximum baud rate in asynchronous mode depends on the sleep mode the device is woken up
from:
• Idle sleep mode: the same as in active mode
Table 24-4. Maximum Total Baud Rate Error in Normal Speed Mode
Baud Rate Frame Size
5 6 7 8 9 10
0 - 28.8 kbps +6.67
-5.88
+5.79
-5.08
+5.11
-4.48
+4.58
-4.00
+4.14
-3.61
+3.78
-3.30
38.4 kbps +6.63
-5.88
+5.75
-5.08
+5.08
-4.48
+4.55
-4.00
+4.12
-3.61
+3.76
-3.30
57.6 kbps +6.10
-5.88
+5.30
-5.08
+4.69
-4.48
+4.20
-4.00
+3.80
-3.61
+3.47
-3.30
76.8 kbps +5.59
-5.88
+4.85
-5.08
+4.29
-4.48
+3.85
-4.00
+3.48
-3.61
+3.18
-3.30
115.2 kbps +4.57
-5.88
+3.97
-5.08
+3.51
-4.48
+3.15
-4.00
+2.86
-3.61
+2.61
-3.30
Table 24-5. Maximum Total Baud Rate Error in Double Speed Mode
Baud Rate Frame Size
5 6 7 8 9 10
0 - 57.6 kbps +5.66
-4.00
+4.92
-3.45
+4.35
-3.03
+3.90
-2.70
+3.53
-2.44
+3.23
-2.22
76.8 kbps +5.59
-4.00
+4.85
-3.45
+4.29
-3.03
+3.85
-2.70
+3.48
-2.44
+3.18
-2.22
115.2 kbps +4.57
-4.00
+3.97
-3.45
+3.51
-3.03
+3.15
-2.70
+2.86
-2.44
+2.61
-2.22
24.10 Multi-Processor Communication Mode
Setting the Multi-Processor Communication mode (MPCMn) bit in UCSRnA enables a filtering function of
incoming frames received by the USART receiver. Frames that do not contain address information will be
ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that
have to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial
bus. The transmitter is unaffected by the MPCMn setting but has to be used differently when it is a part of
a system utilizing the Multi-processor Communication mode.
If the receiver is set up to receive frames that contain five to eight data bits, then the first stop bit indicates
if the frame contains data or address information. If the receiver is set up for frames with 9 data bits, then
the ninth bit (RXB8) is used for identifying address and data frames. When the frame type bit (the first
ATmega328PB
USART - Universal Synchronous Asynchronous R...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 277