Datasheet

D
# (Data+Parity Bit)
R
slow
[%] R
fast
[%] Max. Total Error [%] Recommended Max. Receiver Error [%]
7 94.81 105.11 +5.11/-5.19 ±2.0
8 95.36 104.58 +4.58/-4.54 ±2.0
9 95.81 104.14 +4.14/-4.19 ±1.5
10 96.17 103.78 +3.78/-3.83 ±1.5
Table 24-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1)
D
# (Data+Parity Bit)
R
slow
[%] R
fast
[%] Max Total Error [%] Recommended Max Receiver Error [%]
5 94.12 105.66 +5.66/-5.88 ±2.5
6 94.92 104.92 +4.92/-5.08 ±2.0
7 95.52 104,35 +4.35/-4.48 ±1.5
8 96.00 103.90 +3.90/-4.00 ±1.5
9 96.39 103.53 +3.53/-3.61 ±1.5
10 96.70 103.23 +3.23/-3.30 ±1.0
The recommendations of the maximum receiver baud rate error was made under the assumption that the
receiver and transmitter equally divide the maximum total error.
There are two possible sources for the receivers baud rate error. The receiver’s System Clock (EXTCLK)
will always have some minor instability over the supply voltage range and the temperature range. When
using a crystal to generate the system clock, this is rarely a problem, but for a resonator, the system clock
may differ more than 2% depending on the resonator's tolerance. The second source for the error is more
controllable. The baud rate generator cannot always do an exact division of the system frequency to get
the baud rate wanted. In this case, an UBRRn value that gives an acceptable low error can be used if
possible.
24.9.4 Start Frame Detection
The USART start frame detector can wake up the MCU from Power-down and Standby sleep mode when
it detects a start bit.
When a high-to-low transition is detected on RxDn, the internal 8 MHz oscillator is powered up and the
USART clock is enabled. After start-up, the rest of the data frame can be received, provided that the baud
rate is slow enough in relation to the internal 8 MHz oscillator start-up time. Start-up time of the internal 8
MHz oscillator varies with supply voltage and temperature.
The USART start frame detection works in both asynchronous and synchronous modes. It is enabled by
writing the Start Frame Detection Enable bit (SFDE). If the USART Start Interrupt Enable (RXSIE) bit is
set, the USART Receive Start Interrupt is generated immediately when start is detected.
When using the feature without start interrupt, the start detection logic activates the internal 8 MHz
oscillator and the USART clock while the frame is being received, only. Other clocks remain stopped until
the Receive Complete Interrupt wakes up the MCU.
The maximum baud rate in synchronous mode depends on the sleep mode the device is woken up from:
ATmega328PB
USART - Universal Synchronous Asynchronous R...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 276