Datasheet

/* Get status and 9th bit, then data */
/* from buffer */
status = UCSR0A;
resh = UCSR0B;
resl = UDR0;
/* If error, return -1 */
if ( status & (1<<FE)|(1<<DOR)|(1<<UPE) )
return -1;
/* Filter the 9th bit, then return */
resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);
}
The receive function example reads all the I/O registers into the register file before any computation is
done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept
new data as early as possible.
24.8.3 Receive Compete Flag and Interrupt
The USART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This
flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e.,
does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be
flushed and consequently, the RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIE) in UCSRnB is set, the USART Receive Complete
interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled).
When interrupt-driven data reception is used, the receive complete routine must read the received data
from UDR in order to clear the RXC Flag, otherwise, a new interrupt will occur once the interrupt routine
terminates.
24.8.4 Receiver Error Flags
The USART receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error
(UPE). All can be accessed by reading UCSRnA. Common for the error flags is that they are located in
the receive buffer together with the frame for which they indicate the error status. Due to the buffering of
the error flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O
location changes the buffer read location. Another equality for the error flags is that they cannot be
altered by software doing a write to the flag location. However, all flags must be set to zero when the
UCSRnA is written for upward compatibility of future USART implementations. None of the error flags can
generate interrupts.
The FE flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer.
The FE flag is zero when the stop bit was correctly read as '1', and the FE flag will be one when the stop
bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break
conditions and protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRnC
since the receiver ignores all, except for the first, stop bits. For compatibility with future devices, always
set this bit to zero when writing to UCSRnA.
The DOR flag indicates data loss due to a receiver buffer full condition. A DOR occurs when the receive
buffer is full (two characters), a new character is waiting in the Receive Shift register, and a new start bit
is detected. If the DOR flag is set, one or more serial frames were lost between the last frame read from
UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to
zero when writing to UCSRnA. The DOR flag is cleared when the frame received was successfully moved
from the Shift register to the receive buffer.
ATmega328PB
USART - Universal Synchronous Asynchronous R...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 272