Datasheet

23.5.4 SPI Status Register 1

Name: SPSR1

Offset: 0xAD [ID-000004d0]

Reset: 0x00

Bit 7 6 5 4 3 2 1 0

SPIF1 WCOL1 SPI2X1

Access

R R R/W

Reset 0 0 0

Bit 7 – SPIF1 SPI Interrupt Flag 1

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set

and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this

will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF

set, then accessing the SPI Data Register (SPDR).

Bit 6 – WCOL1 Write Collision Flag 1

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and

the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set and then accessing the

SPI Data Register.

Bit 0 – SPI2X1 Double SPI Speed Bit 1

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in

Master mode (refer to Table 23-5). This means that the minimum SCK period will be two CPU clock

periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4 or lower.

The SPI interface is also used for program memory and EEPROM downloading or uploading. See Serial

Downloading for serial programming and verification.

ATmega328PB

SPI – Serial Peripheral Interface

Datasheet Complete

DS40001906C-page 259