Datasheet

23.5.2 SPI Control Register 1
Name: SPCR1
Offset: 0xAC [ID-000004d0]
Reset: 0x00
Bit 7 6 5 4 3 2 1 0
SPIE1 SPE1 DORD1 MSTR1 CPOL1 CPHA1 SPR1 [1:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 – SPIE1 SPI1 Interrupt Enable
This bit causes the SPI interrupt to be executed if the SPIF bit in the SPSR Register is set and if the
Global Interrupt Enable bit in SREG is set.
Bit 6 – SPE1 SPI1 Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.
Bit 5 – DORD1 Data1 Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
Bit 4 – MSTR1 Master/Slave1 Select
This bit selects the Master SPI mode when written to one, and the Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF
in SPSR will become set. The user will then have to set MSTR to re-enable the SPI Master mode.
Bit 3 – CPOL1 Clock1 Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when
idle. Refer to Figure 23-3 and Figure 23-4 for an example. The CPOL functionality is summarized below:
Table 23-6. CPOL Functionality
CPOL Leading Edge Trailing Edge
0 Rising Falling
1 Falling Rising
Bit 2 – CPHA1 Clock1 Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing
(last) edge of SCK. Refer to Figure 23-3 and Figure 23-4 for an example. The CPHA functionality is
summarized below:
Table 23-7. CPHA1 Functionality
CPHA1 Leading Edge Trailing Edge
0 Sample Setup
1 Setup Sample
ATmega328PB
SPI – Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 256