Datasheet

Bit 2 – CPHA0 Clock0 Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing
(last) edge of SCK. Refer to Figure 23-3 and Figure 23-4 for an example. The CPHA functionality is
summarized below:
Table 23-4. CPHA0 Functionality
CPHA0 Leading Edge Trailing Edge
0 Sample Setup
1 Setup Sample
Bits 1:0 – SPR0 [1:0] SPI0 Clock Rate Select
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect
on the slave. The relationship between SCK and the Oscillator Clock frequency f
osc
is shown in the table
below.
Table 23-5. Relationship Between SCK and Oscillator Frequency
SPI2X SPR0[1] SPR0[0] SCK Frequency
0 0 0 f
osc
/4
0 0 1 f
osc
/16
0 1 0 f
osc
/64
0 1 1 f
osc
/128
1 0 0 f
osc
/2
1 0 1 f
osc
/8
1 1 0 f
osc
/32
1 1 1 f
osc
/64
ATmega328PB
SPI – Serial Peripheral Interface
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 255