Datasheet

Figure 22-2. Output Compare Modulator, Schematic
Pxn
D
Q
R
D
Q
R
D
Q
R
OC3B
OC4B
COM3B0
COM3B1
COM4B0
COM4B1
0
1
D
Q
R
PORTD2 DDRD2
(From waveform
generator)
VCC
Modulator
(From waveform
generator)
T/C3
T/C4
22.2.1 Timing Example
The figure below illustrates the modulator in action. In this example, the Timer/Counter3 is set to operate
in fast PWM mode (non-inverted) and Timer/Counter4 uses CTC waveform mode with toggle Compare
Output mode (COMx[1:0] = 0x1).
Figure 22-3. Output Compare Modulator, Timing Diagram
1 2
OC4B
(CTC Mode)
OC3B
(FPWM Mode)
PD2
(PORTD2 = 0)
PD2
(PORTD2 = 1)
(Period)
3
clk
I/O
In this example, Timer/Counter4 provides the carrier, while the modulating signal is generated by the
Output Compare unit B of the Timer/Counter3.
The resolution of the PWM signal (OC3B) is reduced by the modulation. The reduction factor is equal to
the number of system clock cycles of one period of the carrier (OC4B). In this example, the resolution is
reduced by a factor of two. The reason for the reduction is illustrated in the above figure at the second
and third period of the PD2 output when PORTD2 equals zero. The period 2 high time is one cycle longer
than the period 3 high time, but the result on the PD2 output is equal in both periods.
ATmega328PB
OCM - Output Compare Modulator
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 247