Datasheet

21.11.7 TC2 Interrupt Flag Register
Name: TIFR2
Offset: 0x37
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x17
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
OCF2B OCF2A TOV2
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – OCF2B Timer/Counter 2, Output Compare B Match Flag
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in
OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit
in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the
Timer/Counter 2 Compare match Interrupt is executed.
Bit 1 – OCF2A Timer/Counter 2, Output Compare A Match Flag
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in
OCRA – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit
in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the
Timer/Counter 2 Compare match Interrupt is executed.
Bit 0 – TOV2 Timer/Counter 2, Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter 2. TOV2 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a
logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter 2 Overflow Interrupt Enable), and
TOV2 are set (one), the Timer/Counter 2 Overflow interrupt is executed. In PWM mode, this bit is set
when Timer/Counter 2 changes counting direction at 0x00.
ATmega328PB
TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 242