Datasheet

19.11.27 TC4 Interrupt Flag Register
Name: TIFR4
Offset: 0x39
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x18, 0x19
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
ICF4 OCF4B OCF4A TOV4
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 5 – ICF4 Timer/Counter 4, Input Capture Flag
This flag is set when a capture event occurs on the ICP4 pin. When the Input Capture 4 Register (ICR4)
is set by the WGM[3:0] to be used as the TOP value, the ICF4 Flag is set when the counter reaches the
TOP value.
ICF4 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF4 can
be cleared by writing a logic one to its bit location.
Bit 2 – OCF4B Timer/Counter 4, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT4) value matches the Output Compare
Register B (OCR4B).
Note that a Forced Output Compare (FOC4B) strobe will not set the OCF4B Flag.
OCF4B is automatically cleared when the Output Compare Match B Interrupt Vector is executed.
Alternatively, OCF4B can be cleared by writing a logic one to its bit location.
Bit 1 – OCF4A Timer/Counter 4, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT4) value matches the Output Compare 4
Register A (OCR4A).
Note that a Forced Output Compare (FOC4A) strobe will not set the OCF4A Flag.
OCF4A is automatically cleared when the Output Compare Match A Interrupt Vector is executed.
Alternatively, OCF4A can be cleared by writing a logic one to its bit location.
Bit 0 – TOV4 Timer/Counter 4, Overflow Flag
The setting of this flag is dependent on the WGM[3:0] bits setting. In Normal and CTC modes, the TOV4
Flag is set when the timer overflows. Refer to the Waveform Generation Mode bit description for the
TOV4 Flag behavior when using another WGM[3:0] bit setting.
TOV is automatically cleared when the Timer/Counter 4 Overflow Interrupt Vector is executed.
Alternatively, TOV4 can be cleared by writing a logic one to its bit location.
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 213