Datasheet

19.11.26 TC3 Interrupt Flag Register
Name: TIFR3
Offset: 0x38
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x18
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
The device is a complex microcontroller with more peripheral units than can be supported within the 64
locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit 7 6 5 4 3 2 1 0
ICF3 OCF3B OCF3A TOV3
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 5 – ICF3 Timer/Counter3, Input Capture Flag
This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register (ICR3) is
set by the WGM33:0 to be used as the TOP value, the ICF3 Flag is set when the counter reaches the
TOP value.
ICF3 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF3 can
be cleared by writing a logic one to its bit location.
Bit 2 – OCF3B Timer/Counter3, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare
Register B (OCR3B).
Note that a Forced Output Compare (FOC3B) strobe will not set the OCF3B Flag.
OCF3B is automatically cleared when the Output Compare Match B Interrupt Vector is executed.
Alternatively, OCF3B can be cleared by writing a logic one to its bit location.
Bit 1 – OCF3A Timer/Counter3, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare
Register A (OCR3A).
Note that a Forced Output Compare (FOC3A) strobe will not set the OCF3A Flag.
OCF3A is automatically cleared when the Output Compare Match A Interrupt Vector is executed.
Alternatively, OCF3A can be cleared by writing a logic one to its bit location.
Bit 0 – TOV3 Timer/Counter1, Overflow Flag
The setting of this flag is dependent on the WGM33:0 bits setting. In Normal and CTC modes, the TOV3
Flag is set when the timer overflows. Refer to Table 19-6 for the TOV3 Flag behavior when using another
WGM33:0 bit setting.
TOV3 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV3 can be cleared by writing a logic one to its bit location.
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 212