Datasheet

19.11.24 Timer/Counter 4 Interrupt Mask Register

Name: TIMSK4

Offset: 0x72

Reset: 0x00

Property: -

Bit 7 6 5 4 3 2 1 0

ICIE4 OCIE4B OCIE4A TOIE4

Access

R/W R/W R/W R/W

Reset 0 0 0 0

Bit 5 – ICIE4 Timer/Counter 4, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the

Timer/Counter 4 Input Capture interrupt is enabled. The corresponding Interrupt Vector is executed when

the ICF4 Flag, located in TIFR4, is set.

Bit 2 – OCIE4B Timer/Counter 4, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the

Timer/Counter n Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector is

executed when the OCF4B Flag, located in TIFR4, is set.

Bit 1 – OCIE4A Timer/Counter 4, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the

Timer/Counter n Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector is

executed when the OCF4A Flag, located in TIFR4, is set.

Bit 0 – TOIE4 Timer/Counter 4, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the

Timer/Counter 4 Overflow interrupt is enabled. The corresponding Interrupt Vector is executed when the

TOV Flag, located in TIFR4, is set.

ATmega328PB

TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM

Datasheet Complete

DS40001906C-page 210