Datasheet

19.11.15 TC4 Control Register A
Name: TCCR4A
Offset: 0xA0
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
COM4A[1:0] COM4B[1:0] WGM4[1:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 4:5, 6:7 – COM4 Compare Output Mode for Channel
The COM4A[1:0] and COM4B[1:0] control the Output Compare pins (OC4A and OC4B respectively)
behavior. If one or both of the COM4A[1:0] bits are written to one, the OC4A output overrides the normal
port functionality of the I/O pin it is connected to. If one or both of the COM4B[1:0] bit are written to one,
the OC4B output overrides the normal port functionality of the I/O pin it is connected to. However, note
that the Data Direction Register (DDR) bit corresponding to the OC4A or OC4B pin must be set in order
to enable the output driver.
When the OC4A or OC4B is connected to the pin, the function of the COM4x[1:0] bits is dependent on
the WGM4[3:0] bits setting. The table below shows the COM4n[1:0] bit functionality when the WGM4[3:0]
bits are set to a Normal or a CTC mode (non-PWM).
For OC3B or OC4B when not using the Output Compare Modulator, PORTD2 must also be set in order to
enable the output.
Table 19-13. Compare Output Mode, Non-PWM
COM4A[1]/
COM4B[1]
COM4A[0]/
COM4B[0]
Description
0 0 Normal port operation, OC4A/OC4B disconnected.
0 1 Toggle OC4A/OC4B on Compare Match.
1 0 Clear OC4A/OC4B on Compare Match (Set output to low
level).
1 1 Set OC4A/OC4B on Compare Match (Set output to high
level).
The table below shows the COM4x[1:0] bit functionality when the WGM4[3:0] bits are set to the fast PWM
mode.
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 198