Datasheet

Table 19-11. Waveform Generation Mode Bit Description
Mode WGM3[3] WGM3[2]
(CTC1)
(1)
WGM3[1]
(PWM1[1])
(1)
WGM3[0]
(PWM1[0])
(1)
Timer/
Counter
Mode of
Operation
TOP Update of
OCR1x at
TOV1 Flag
Set on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
1 0 0 0 1 PWM, Phase
Correct, 8-bit
0x00FF TOP BOTTOM
2 0 0 1 0 PWM, Phase
Correct, 9-bit
0x01FF TOP BOTTOM
3 0 0 1 1 PWM, Phase
Correct, 10-bit
0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCR3A Immediate MAX
5 0 1 0 1 Fast PWM, 8-
bit
0x00FF BOTTOM TOP
6 0 1 1 0 Fast PWM, 9-
bit
0x01FF BOTTOM TOP
7 0 1 1 1 Fast PWM, 10-
bit
0x03FF BOTTOM TOP
8 1 0 0 0 PWM, Phase
and Frequency
Correct
ICR1 BOTTOM BOTTOM
9 1 0 0 1 PWM, Phase
and Frequency
Correct
OCR3A BOTTOM BOTTOM
10 1 0 1 0 PWM, Phase
Correct
ICR3 TOP BOTTOM
11 1 0 1 1 PWM, Phase
Correct
OCR3A TOP BOTTOM
12 1 1 0 0 CTC ICR3 Immediate MAX
13 1 1 0 1 Reserved - - -
14 1 1 1 0 Fast PWM ICR3 BOTTOM TOP
15 1 1 1 1 Fast PWM OCR3A BOTTOM TOP
Note:
1. The CTC1 and PWM1[1:0] bit definition names are obsolete. Use the WGM3[2:0] definitions.
However, the functionality and location of these bits are compatible with previous versions of the
timer.
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 190