Datasheet

19.11.8 TC3 Control Register A
Name: TCCR3A
Offset: 0x90
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
COM3A[1:0] COM3B[1:0] WGM3[1:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 4:5, 6:7 – COM3 Compare Output Mode for Channel
The COM3A[1:0] and COM3B[1:0] control the Output Compare pins (OC3A and OC3B respectively)
behavior. If one or both of the COM3A[1:0] bits are written to one, the OC3A output overrides the normal
port functionality of the I/O pin it is connected to. If one or both of the COM3B[1:0] bit are written to one,
the OC3B output overrides the normal port functionality of the I/O pin it is connected to. However, note
that the Data Direction Register (DDR) bit corresponding to the OC3A or OC3B pin must be set in order
to enable the output driver.
When the OC3A or OC3B is connected to the pin, the function of the COM3n[1:0] bits is dependent on
the WGM3[3:0] bits setting. The table below shows the COM3n[1:0] bit functionality when the WGM3[3:0]
bits are set to a Normal or a CTC mode (non-PWM).
For OC3B or OC4B when not using the Output Compare Modulator, PORTD2 must also be set in order to
enable the output.
Table 19-8. Compare Output Mode, Non-PWM
COM3A[1]/
COM3B[1]
COM3A[0]/
COM3B[0]
Description
0 0 Normal port operation, OC3A/OC3B disconnected.
0 1 Toggle OC3A/OC3B on Compare Match.
1 0 Clear OC3A/OC3B on Compare Match (Set output to low
level).
1 1 Set OC3A/OC3B on Compare Match (Set output to high
level).
The table below shows the COM1x[1:0] bit functionality when the WGM3[3:0] bits are set to the fast PWM
mode.
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 188