Datasheet

and the falling slopes will always be equal. This gives symmetrical output pulses and is, therefore,
frequency correct.
Using the ICRn register for defining TOP works well when using fixed TOP values. By using ICRn, the
OCRnA register is free to be used for generating a PWM output on OCnA. However, if the base PWM
frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better
choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on
the OCnx pins. Setting the COMnx[1:0] bits to 0x2 will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COMnx[1:0] to 0x3 (see the description of TCCRA.COMnx).
The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as
output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx register at the
compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the
OCnx register at compare match between OCRnx and TCNTn when the counter decrements. The PWM
frequency for the output when using phase and frequency correct PWM can be calculated by the
following equation:

OCnxPFCPWM
=

clk_I/O
2    TOP
Note:
• The “n” in the register and bit names indicates the device number (n = 1, 3, 4 for Timer/Counter 1,
3, 4), and the “x” indicates output compare unit (A/B).
• N represents the prescale divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx register represent special cases when generating a PWM waveform
output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be
continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For
inverted PWM the output will have the opposite logic values. If OCRnA is used to define the TOP value
(WGMn[3:0]=0x9) and COMnA[1:0]=0x1, the OCnA output will toggle with a 50% duty cycle.
19.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
Tn
) is therefore shown as a clock
enable signal in the following figures. The figures include information on when interrupt flags are set, and
when the OCRnx is updated with the OCRnx buffer value (only for modes utilizing double buffering). The
first figure shows a timing diagram for the setting of OCFnx.
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 175