Datasheet

The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or
OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum
resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the
following equation:

PFCPWM
=
log TOP+1
log 2
In phase and frequency correct PWM mode the counter is incremented until the counter value matches
either the value in ICRn (WGMn[3:0]=0x8), or the value in OCRnA (WGMn[3:0]=0x9). The counter has
then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one
timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown
below. The figure shows phase and frequency correct PWM mode when OCRnA or ICRn is used to
define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks
on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx interrupt flag
will be set when a compare match occurs.
Figure 19-8. Phase and Frequency Correct PWM Mode, Timing Diagram
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TCNTn
Period
OCnx
OCnx
(COMnx[1:0] = 0x2)
(COMnx[1:0] = 0x3)
Note: The “n” in the register and bit names indicates the device number (n = 1, 3, 4 for Timer/Counter 1,
3, 4), and the “x” indicates output compare unit (A/B).
The Timer/Counter Overflow flag (TOVn) is set at the same timer clock cycle as the OCRnx registers are
updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn is used for defining the
TOP value, the OCnA or ICFn Flag set when TCNTn has reached TOP. The interrupt flags can then be
used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the
value of all of the Compare registers. If the TOP value is lower than any of the Compare registers, a
compare match will never occur between the TCNTn and the OCRnx.
As shown in the timing diagram above, the output generated is, in contrast to the phase correct mode,
symmetrical in all periods. Since the OCRnx registers are updated at BOTTOM, the length of the rising
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 174