Datasheet

Correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope
operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to
BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the
compare match between TCNTn and OCRnx while up-counting, and set on the compare match while
down-counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation
has lower maximum operation frequency than single-slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the Phase Correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by
either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the
maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated
by using the following equation:

PCPWM
=
log TOP+1
log 2
In Phase Correct PWM mode the counter is incremented until the counter value matches either one of the
fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn[3:0]= 0x1, 0x2, or 0x3), the value in ICRn
(WGMn[3:0]=0xA), or the value in OCRnA (WGMn[3:0]=0xB). The counter has then reached the TOP and
changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing
diagram for the Phase Correct PWM mode is shown below, using OCRnA or ICRn to define TOP. The
TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNTn
slopes mark compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a
compare match occurs.
Figure 19-7. Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx[1:0]] = 0x2)
(COMnx[1:0] = 0x3)
Note: The “n” in the register and bit names indicates the device number (n = 1, 3, 4 for Timer/Counter 1,
3, 4), and the “x” indicates output compare unit (A/B).
The Timer/Counter Overflow flag (TOVn) is set each time the counter reaches BOTTOM. When either
OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accordingly at the same
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 172