Datasheet

When changing the TOP value the program must ensure that the new TOP value is higher or equal to the
value of all of the Compare registers. If the TOP value is lower than any of the Compare registers, a
compare match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP
values the unused bits are masked to zero when any of the OCRnx registers are written.
The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value.
The ICRn register is not double buffered. This means that if ICRn is changed to a low value when the
counter is running with none or a low prescaler value, there is a risk that the new ICRn value written is
lower than the current value of TCNTn. As result, the counter will miss the compare match at the TOP
value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at
0x0000 before the compare match can occur. The OCRnA Register, however, is double buffered. This
feature allows the OCRnA I/O location to be written any time. When the OCRnA I/O location is written the
value written will be put into the OCRnA Buffer register. The OCRnA Compare register will then be
updated with the value in the Buffer register at the next timer clock cycle the TCNTn matches TOP. The
update is performed at the same timer clock cycle as the TCNTn is cleared and the TOVn flag is set.
Using the ICRn register for defining TOP works well when using fixed TOP values. By using ICRn, the
OCRnA is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency
is actively changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due
to its double buffer feature.
In Fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Writing
the COMnx[1:0] bits to 0x2 will produce an inverted PWM and a non-inverted PWM output can be
generated by writing the COMnx[1:0] to 0x3. The actual OCnx value will only be visible on the port pin if
the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by
setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn, and clearing
(or setting) the OCnx register at the timer clock cycle the counter is cleared (changes from TOP to
BOTTOM).
The PWM frequency for the output can be calculated by the following equation:

OCnxPWM
=

clk_I/O
 
1 + TOP
Note:
• The “n” in the register and bit names indicates the device number (n = 1, 3, 4 for Timer/Counter 1,
3, 4), and the “x” indicates output compare unit (A/B).
• N represents the prescale divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx registers represent special cases when generating a PWM waveform
output in the Fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow
spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP will result in a constant high or
low output (depending on the polarity of the output which is controlled by COMnx[1:0]).
A frequency waveform output with 50% duty cycle can be achieved in Fast PWM mode by selecting
OCnA to toggle its logical level on each compare match (COMnA[1:0]=0x1). This applies only if OCRnA is
used to define the TOP value (WGMn[3:0]=0xF). The waveform generated will have a maximum
frequency of f
OCnA
= f
clk_I/O
/2 when OCRnA is set to zero (0x0000). This feature is similar to the OCnA
toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the Fast
PWM mode.
19.9.4 Phase Correct PWM Mode
The Phase Correct Pulse Width Modulation or Phase Correct PWM modes (WGMn[3:0]= 0x1, 0x2, 0x3,
0xA, and 0xB) provide a high resolution, phase correct PWM waveform generation option. The Phase
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 171