Datasheet

In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the compare match
between TCNTn and OCRnx and set at BOTTOM. In inverting Compare Output mode output is set on
compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of
the Fast PWM mode can be twice as high as the phase correct, and phase and frequency correct PWM
modes that use dual-slope operation. This high frequency makes the Fast PWM mode well suited for
power regulation, rectification, and DAC applications. High frequency allows physically small sized
external components (coils, capacitors), hence reduces total system cost.
The PWM resolution for Fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA.
The minimum resolution allowed is 2-bit (ICRn or OCRnA register set to 0x0003), and the maximum
resolution is 16-bit (ICRn or OCRnA registers set to MAX). The PWM resolution in bits can be calculated
by using the following equation:

FPWM
=
log TOP+1
log 2
In Fast PWM mode the counter is incremented until the counter value matches either one of the fixed
values 0x00FF, 0x01FF, or 0x03FF (WGMn[3:0] = 0x5, 0x6, or 0x7), the value in ICRn (WGMn[3:0]=0xE),
or the value in OCRnA (WGMn[3:0]=0xF). The counter is then cleared at the following timer clock cycle.
The timing diagram for the Fast PWM mode using OCRnA or ICRn to define TOP is shown below. The
TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNTn
slopes mark compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a
compare match occurs.
Figure 19-6. Fast PWM Mode, Timing Diagram
TCNTn
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 7
Period
2 3 4 5 6 8
OCnx
OCnx
(COMnx[1:0] = 0x2)
(COMnx[1:0] = 0x3)
Note: The “n” in the register and bit names indicates the device number (n = 1, 3, 4 for Timer/Counter 1,
3, 4), and the “x” indicates output compare unit (A/B).
The Timer/Counter Overflow flag (TOVn) is set each time the counter reaches TOP. In addition, when
either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag is set at the same timer
clock cycle TOVn is set. If one of the interrupts are enabled, the interrupt handler routine can be used for
updating the TOP and compare values.
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 170