Datasheet

Both the Input Capture Pin (ICPn) and the Analog Comparator Output (ACO) inputs are sampled using
the same technique as for the Tn pin. The edge detector is identical. However, when the noise canceler is
enabled, additional logic is inserted before the edge detector, which increases the delay by four system
clock cycles. The input of the noise canceler and edge detector is always enabled unless the Timer/
Counter is set in a Waveform Generation mode that uses ICRn to define TOP.
An input capture can be triggered by software by controlling the port of the ICPn pin.
Related Links
Timer/Counter 0, 1, 3, 4 Prescalers
19.6.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise
canceler input is monitored over four samples, and all four must be equal for changing the output that in
turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler bit in the Timer/Counter
Control Register B (TCCRnB.ICNC). When enabled, the noise canceler introduces an additional delay of
four system clock cycles between a change applied to the input and the update of the ICRn Register. The
noise canceler uses the system clock and is therefore not affected by the prescaler.
19.6.3 Using the Input Capture Unit
The main challenge when using the input capture unit is to assign enough processor capacity for handling
the incoming events. The time between two events is critical. If the processor has not read the captured
value in the ICRn before the next event occurs, the ICRn will be overwritten with a new value. In this case
the result of the capture will be incorrect.
When using the input capture interrupt, the ICRn should be read as early in the interrupt handler routine
as possible. Even though the input capture interrupt has relatively high priority, the maximum interrupt
response time is dependent on the maximum number of clock cycles it takes to handle any of the other
interrupt requests.
Using the input capture unit in any mode of operation when the TOP value (resolution) is actively
changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each
capture. Changing the edge sensing must be done as early as possible after the ICRn has been read.
After a change of the edge, the ICF must be cleared by software (writing a logical one to the I/O bit
location). For measuring frequency only, the clearing of the ICF is not required (if an interrupt handler is
used).
19.7 Compare Match Output Unit
The Compare Output mode (TCCRnA.COMnx[1:0]) bits have two functions. The waveform generator
uses the TCCRnA.COMnx[1:0] bits for defining the Output Compare (OCnx) state at the next compare
match. Secondly the TCCRnA.COMnx[1:0] bits control the OCnx pin output source. The figure below
shows a simplified schematic of the logic affected by the TCCRnA.COMnx[1:0] bit setting. The I/O
registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port
control registers (DDR and PORT) that are affected by the TCCRnA.COMnx[1:0] bits are shown. When
referring to the OCnx state, the reference is for the internal OCnx register, not the OCnx pin. If a System
Reset occurs, the OCnx register is reset to “0”.
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 165