Datasheet

Signal Name Description
Clear Clear TCNTn (set all bits to zero).
clk
Tn
Timer/Counter clock.
TOP Signalize that TCNTn has reached maximum value.
BOTTOM Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing the
upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH
register can only be accessed indirectly by the CPU. When the CPU does an access to the TCNTnH I/O
location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated
with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the temporary register
value when TCNTnL is written. This allows the CPU to read or write the entire 16-bit counter value within
one clock cycle via the 8-bit data bus.
Note: That there are special cases when writing to the TCNTn register while the counter is counting will
give unpredictable results. These special cases are described in the sections where they are of
importance.
Depending on the selected mode of operation, the counter is cleared, incremented, or decremented at
each timer clock (clk
Tn
). The clock clk
Tn
can be generated from an external or internal clock source, as
selected by the clock select bits in the Timer/Countern control register B (TCCRnB.CS[2:0]). When no
clock source is selected (CS[2:0]=0x0) the timer is stopped. However, the TCNTn value can be accessed
by the CPU, independent of whether clk
Tn
is present or not. A CPU write overrides (i.e., has priority over)
all counter clear or count operations.
The counting sequence is determined by the setting of the waveform generation mode bits in the Timer/
Counter Control Registers A and B (TCCRnB.WGMn[3:2] and TCCRnA.WGMn[1:0]). There are close
connections between how the counter behaves (counts) and how waveforms are generated on the
Output Compare outputs OC0x. For more details about advanced counting sequences and waveform
generation, see Modes of Operation.
The Timer/Counter Overflow Flag in the TCn Interrupt Flag Register (TIFRn.TOV) is set according to the
mode of operation selected by the WGMn[3:0] bits. TOV can be used for generating a CPU interrupt.
19.6 Input Capture Unit
The Timer/Countern incorporates an input capture unit that can capture external events and give them a
time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can
be applied via the ICPn pin or alternatively, via the analog-comparator unit. The time-stamps can then be
used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively, the time-
stamps can be used for creating a log of the events.
The input capture unit is illustrated by the block diagram below. The elements of the block diagram that
are not directly a part of the input capture unit are gray shaded. The lower case “n” in register and bit
names indicates the Timer/Counter number.
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 163