Datasheet

Table 19-1. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x0 for 8-bit counters, or 0x00 for
16-bit counters).
MAX The counter reaches its MAXimum when it becomes 0xF (decimal 15, for 8-bit counters) or
0xFF (decimal 255, for 16-bit counters).
TOP The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value MAX or the value stored in
the OCRnA Register. The assignment is dependent on the mode of operation.
19.2.2 Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRA/B), and Input Capture Register (ICRn)
are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These
procedures are described in section Accessing 16-bit Timer/Counter Registers.
The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no CPU access
restrictions. Interrupt requests (abbreviated to Int.Req. in the block diagram) signals are all visible in the
Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Interrupt Mask
Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn
pin. The clock select logic block controls which clock source and edge the Timer/Counter uses to
increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The
output from the clock select logic is referred to as the timer clock (clk
Tn
).
The double buffered Output Compare Registers (OCRnA/B) are compared with the Timer/Counter value
at all time. The result of the compare can be used by the waveform generator to generate a PWM or
variable frequency output on the Output Compare pin (OCnA/B). See Output Compare Units. The
compare match event will also set the Compare Match Flag (OCFnA/B), which can be used to generate
an output compare interrupt request.
The input capture register can capture the Timer/Counter value at a given external (edge triggered) event
on either the Input Capture pin (ICPn) or on the analog comparator pins. The input capture unit includes a
digital filtering unit (Noise canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either
the OCRnA register, the ICRn register, or by a set of fixed values. When using OCRnA as TOP value in a
PWM mode, the OCRnA register cannot be used for generating a PWM output. However, the TOP value
will, in this case, be double buffered allowing the TOP value to be changed in runtime. If a fixed TOP
value is required, the ICRn register can be used as an alternative, freeing the OCRnA to be used as
PWM output.
19.3 Accessing 16-bit Timer/Counter Registers
The TCNTn, OCRnA/B, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit
data bus. The 16-bit register must be accessed byte-wise, using two read or write operations. Each 16-bit
timer has a single 8-bit TEMP register for temporary storing of the high byte of the 16-bit access. The
same temporary register is shared between all 16-bit registers within each 16-bit timer.
Accessing the low byte triggers the 16-bit read or write operation: When the low byte of a 16-bit register is
written by the CPU, the high byte that is currently stored in TEMP and the low byte being written are both
copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by
ATmega328PB
TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001906C-page 159