Datasheet

18.9.7 TC0 Output Compare Register B

Name: OCR0B

Offset: 0x48

Reset: 0x00

Property: When addressing as I/O register: address offset is 0x28

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

The device is a complex microcontroller with more peripheral units than can be supported within the 64

locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in

SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Bit 7 6 5 4 3 2 1 0

OCR0B[7:0]

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – OCR0B[7:0] Output Compare 0 B

The output compare register B contains an 8-bit value that is continuously compared with the counter

value (TCNT0). A match can be used to generate an output compare interrupt or to generate a waveform

output on the OC0B pin.

ATmega328PB

TC0 - 8-bit Timer/Counter0 with PWM

Datasheet Complete

DS40001906C-page 156