Datasheet

18.9.5 TC0 Counter Value Register

Name: TCNT0

Offset: 0x46

Reset: 0x00

Property: When addressing as I/O Register: address offset is 0x26

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

The device is a complex microcontroller with more peripheral units than can be supported within the 64

locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 in

SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Bit 7 6 5 4 3 2 1 0

TCNT0[7:0]

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – TCNT0[7:0] TC0 Counter Value

The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter

unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following

timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a

compare match between TCNT0 and the OCR0x registers.

ATmega328PB

TC0 - 8-bit Timer/Counter0 with PWM

Datasheet Complete

DS40001906C-page 154